Sleep state transitioning
First Claim
1. In a system comprising a processor, a first memory, a first memory controller, and a second memory, a method for transitioning between an awake state and a sleep state comprising:
- detecting a trigger to transition from the sleep state to the awake state;
initializing the first memory controller in response to the detecting, the initializing comprising executing software in the second memory; and
executing software in the first memory after the initializing.
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Abstract
A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
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Citations
30 Claims
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1. In a system comprising a processor, a first memory, a first memory controller, and a second memory, a method for transitioning between an awake state and a sleep state comprising:
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detecting a trigger to transition from the sleep state to the awake state;
initializing the first memory controller in response to the detecting, the initializing comprising executing software in the second memory; and
executing software in the first memory after the initializing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. In a system comprising a processor, a first memory, a first memory controller, and a second memory, wherein the processor and memory controller have inputs for receiving respective clock signals, and the first memory stores operating system software, a method for transitioning between an awake state and a sleep state comprising:
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preparing, under control of the operating system software, for a transition from the awake state to the sleep state, the preparing including configuring the address space mapping to point to the second memory following the detecting;
preventing the receiving of the respective clock signals;
transitioning to the sleep state;
detecting a trigger to transition from the sleep state to the awake state;
initializing the first memory controller in response to the detecting, the initializing comprising executing BIOS software in the second memory;
executing operating system software after the initializing. - View Dependent Claims (18, 19)
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20. A system comprising:
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a processor having an awake state and a sleep state;
a first memory;
a first memory controller;
a second memory; and
software stored in the second memory that executes to initialize the first memory controller responsive to a trigger signal signaling a transition from the sleep state to the awake state. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A portable computer system comprising:
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a power storage medium;
a display;
a processor;
a processor clock;
a first memory;
a first memory controller;
a second memory;
wherein the system includes an awake state and a sleep state;
wherein the processor and first memory controller are not clocked in the sleep state; and
wherein software in the second memory initializes the first memory controller responsive to a transition from the sleep state to the awake state. - View Dependent Claims (30)
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Specification