Systems and methods for providing error correction code testing functionality
First Claim
Patent Images
1. A memory controller, comprising:
- a cache line processing block for processing a cache line into a plurality of segments;
an error correction code (ECC) generation block that forms ECC code words for each of said plurality of segments for storage in a plurality of memory components;
an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and
an error seeding block that enables a respective error to be inserted into each ECC code word of said cache line in response to a plurality of error registers.
4 Assignments
0 Petitions
Accused Products
Abstract
In one embodiment, a memory controller comprises a cache line processing block for processing a cache line into a plurality of segments, an error correction code (ECC) generation block that forms ECC code words for each of the plurality of segments for storage in a plurality of memory components, an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from the plurality of memory components, and an error seeding block that enables a respective error to be inserted into each ECC code word of the cache line in response to a plurality of error registers.
-
Citations
20 Claims
-
1. A memory controller, comprising:
-
a cache line processing block for processing a cache line into a plurality of segments;
an error correction code (ECC) generation block that forms ECC code words for each of said plurality of segments for storage in a plurality of memory components;
an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and
an error seeding block that enables a respective error to be inserted into each ECC code word of said cache line in response to a plurality of error registers. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method for operating a memory controller, comprising:
-
processing a cache line into a plurality of segments;
generating ECC code words for each of said plurality of segments;
seeding a respective error into each ECC code word of said cache line in response to a plurality of error registers of said memory controller;
storing said ECC code words in a plurality of memory components;
retrieving said ECC code words from said plurality of memory components; and
validating an ECC algorithm by attempting to correct each respective inserted error of said ECC code words as an erasure error. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
-
-
16. A memory controller, comprising:
-
means for processing a cache line into a plurality of segments;
means for generating ECC code words for each of said plurality of segments for storage in a plurality of memory components;
means for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from said plurality of memory components; and
means for inserting a respective error into each ECC code word of said cache line in response to a plurality of error registers, wherein said means for inserting is operable before said means for correcting. - View Dependent Claims (17, 18, 19, 20)
-
Specification