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Constrained optimization with linear constraints to remove overlap among cells of an integrated circuit

  • US 20040225982A1
  • Filed: 05/09/2003
  • Published: 11/11/2004
  • Est. Priority Date: 05/09/2003
  • Status: Active Grant
First Claim
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1. A computer implemented method for placing circuit elements of an integrated circuit design comprising:

  • accessing a layout of said design with an initial cell placement;

    generating a plurality of linear inequalities to represent allowable placements of a plurality of cells of a layout to remove cell overlap; and

    minimizing an objective function measuring cell movement subject to constraints of said plurality of inequalities to arrive at a new cell placement, said objective function minimizing cell movement from said initial cell placement.

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