Plasma density, energy and etch rate measurements at bias power input and real time feedback control of plasma source and bias power

• US 20040226657A1
• Filed: 05/16/2003
• Published: 11/18/2004
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hoffman, Daniel J.
• Granted Patent: US 7,247,218 B2
• Time in Patent Office: Days
• US Class Current: 156/345.28
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge

Abstract

A plasma reactor process measurement instrument includes an input phase processor receiving wafer bias voltage, current and power and computing an input impedance, an input current and an input voltage to the transmission line; a transmission line processor for computing a junction admittance of a junction between the transmission line and the conductive grid from the input impedance, input current and input voltage and from parameters of the transmission line; a grid-to-ground transformation unit for providing shunt electrical quantities of a shunt capacitance between the grid and a ground plane; a grid-to-wafer transformation unit for providing load electrical quantities of a load capacitance between the grid and the wafer; and, a combined transformation processor for computing the at least one of the etch rate, plasma ion density and wafer voltage from the junction admittance, the shunt electrical quantities, the load electrical quantities and a frequency of the RF power generator.

Claims

1. An instrument for measuring at least one of:

(a) etch rate, (b) plasma ion density, (c) wafer voltage, in a plasma reactor during processing of a semiconductor wafer on a workpiece support within a chamber of the plasma reactor containing a plasma, said reactor including an RF power generator coupled from an impedance match circuit through a transmission line to a conductive grid within the workpiece support, said instrument comprising;

an input phase processor connected to sense voltage, current and power at said impedance match network for computing, from said voltage, current and power, an input impedance, an input current and an input voltage to said transmission line;

a transmission line processor for computing a junction admittance of a junction between said transmission line and said conductive grid from said input impedance, input current and input voltage and from parameters of said transmission line;

a grid-to-ground transformation unit for providing shunt electrical quantities of a shunt capacitance between said grid and a ground plane;

a grid-to-wafer transformation unit for providing load electrical quantities of a load capacitance between said grid and said wafer; and

a combined transformation processor for computing the at least one of said etch rate, plasma ion density and wafer voltage from said junction admittance, said shunt electrical quantities, said load electrical quantities and a frequency of said RF power generator.

2. The instrument of claim 1 wherein said instrument is further for measuring wafer current, and wherein said combined transformation processor further computes said wafer current from said junction admittance, said shunt electrical quantities and said load electrical quantities.

3. The instrument of claim 1 wherein said input phase processor, said transmission line processor, said grid-to-ground processor, said grid-to-wafer processor and said combined transformation processor comprise shared resources within a common microprocessor.

4. The instrument of claim 1 wherein said parameters of said transmission line processor comprise a length of said transmission line, a characteristic impedance of said transmission line and a complex loss factor of said transmission line.

5. The instrument of claim 1 wherein said shunt electrical quantities are computed from the size of a grid-to-ground gap length, an area of said wafer, a grid-to-ground dielectric constant and a grid-to-ground conductive loss component.

6. The instrument of claim 5 wherein said grid-to-ground transformation unit comprises a memory storing said shunt electrical quantities.

7. The instrument of claim 6 wherein said grid-to-ground transformation unit further comprises a processor for computing said shunt electrical quantities.

8. The instrument of claim 1 wherein said load electrical quantities are computed from a grid-to-wafer gap length, an area of said wafer, a grid-to-wafer dielectric constant and a grid-to-wafer conductive loss component.

9. The instrument of claim 8 wherein said grid-to-wafer transformation unit comprises a memory storing said load electrical quantities.

10. The instrument of claim 9 wherein said grid-to-wafer transformation unit further comprises a processor for computing said load electrical quantities.

11. The instrument of claim 1 wherein said combined transformation processor computes said wafer voltage and an imaginary part of said plasma admittance comprising a plasma susceptance, and computes at least one of said ion density and etch rate from said wafer voltage and said plasma susceptance.

12. A plasma reactor comprising:

a vacuum chamber and a wafer support pedestal within said chamber for supporting a wafer to be processed within said chamber;

a process gas inlet for furnishing process gases into said chamber;

an overhead RF power applicator near a ceiling of said chamber and overlying said wafer support pedestal, a plasma RF source power supply and a first impedance match circuit connected between said plasma RF source power supply and said overhead electrode;

a plasma RF bias power supply and a second impedance match circuit connected between said plasma RF bias power supply and said wafer support pedestal, said second impedance match circuit having sensor circuits providing measurement signals representing bias power, voltage and current at said impedance match circuit;

a measurement instrument for converting said measurement signals representing bias power, voltage and current at said impedance match circuit into a wafer voltage measurement signal representing the voltage on a wafer supported on said wafer pedestal and an ion density measurement signal representing plasma ion density in said chamber;

a bias power feedback controller comprising;

(a) a circuit furnishing a wafer voltage target value,

(b) a subtractor for computing a wafer voltage error between said wafer voltage measurement signal and said wafer voltage target value, and

(c) a circuit for generating a bias power control signal from said wafer voltage error and applying said bias power control signal to said plasma RF bias power supply so as to govern the output power of said plasma RF bias power supply in a manner that tends to reduce said wafer voltage error.

13. The plasma reactor of claim 12 wherein said circuit for generating a bias power control signal comprises:

a circuit furnishing a bias power feedback gain factor; and

a multiplier for multiplying said wafer voltage error by said bias power feedback gain factor to produce said bias power control signal.

14. The plasma reactor of claim 12 wherein said circuit furnishing a wafer voltage target value comprises a memory wherein said wafer voltage target value is stored.

15. The plasma reactor of claim 12 wherein said measurement instrument further converts said bias power, voltage and current measurement signals into an ion density measurement signal representing plasma ion density in said chamber, said plasma reactor further comprising a source power feedback controller, said source power feedback controller comprising:

(a) a circuit furnishing an ion density target value,

(b) a subtractor for computing an ion density error between said ion density measurement signal and said ion density target value, and

(c) a circuit for generating a source power control signal from said ion density error and applying said source power control signal to said plasma RF source power supply so as to govern the output power of said plasma RF source power supply in a manner that tends to reduce said ion density error.

16. The plasma reactor of claim 15 wherein said circuit for generating a source power control signal comprises:

a circuit furnishing a source power feedback gain factor; and

a multiplier for multiplying said ion density error by said source power feedback gain factor to produce said source power control signal.

17. The plasma reactor of claim 15 wherein said circuit furnishing an ion density target value comprises a memory wherein said ion density target value is stored.

18. The plasma reactor of claim 12 wherein said measurement instrument further converts said bias power, voltage and current measurement signals into an etch rate measurement signal representing etch rate on said wafer in said chamber, said reactor further comprising a source power feedback controller, said source power feedback controller comprising:

(a) a circuit furnishing an etch rate target value,

(b) a subtractor for computing an etch rate error between said etch rate measurement signal and said etch rate target value, and

(c) a circuit for generating a source power control signal from said etch rate error and applying said source power control signal to said plasma RF source power supply so as to govern the output power of said plasma RF source power supply in a manner that tends to reduce said etch rate error.

19. The plasma reactor of claim 15 wherein said circuit for generating a source power control signal comprises:

a circuit furnishing a source power feedback gain factor; and

a multiplier for multiplying said etch rate error by said source power feedback gain factor to produce said source power control signal.

20. The plasma reactor of claim 15 wherein said circuit furnishing an etch rate target value comprises a memory wherein said etch rate target value is stored.

21. The plasma reactor of claim 15 wherein said RF bias power generator is coupled from said second impedance match circuit through a transmission line to a conductive grid within the workpiece support, said measurement instrument comprising:

an input phase processor for computing, from the measurement signals representing bias power, voltage and current at said second impedance match circuit, an input impedance, an input current and an input voltage to said transmission line;

a transmission line processor for computing a junction admittance of a junction between said transmission line and said conductive grid from said input impedance, input current and input voltage and from parameters of said transmission line;

a grid-to-ground transformation unit for providing shunt electrical quantities of a shunt capacitance between said grid and a ground plane;

a grid-to-wafer transformation unit for providing load electrical quantities of a load capacitance between said grid and said wafer; and

a combined transformation processor for computing the at least one of said etch rate, plasma ion density and wafer voltage from said junction admittance, said shunt electrical quantities, said load electrical quantities and a frequency of said RF power generator.

22. The instrument of claim 21 wherein said instrument is further for measuring wafer current, and wherein said combined transformation processor further computes said wafer current from said junction admittance, said shunt electrical quantities and said load electrical quantities.

23. The instrument of claim 21 wherein said input phase processor, said transmission line processor, said grid-to-ground processor, said grid-to-wafer processor and said combined transformation processor comprise shared resources within a common microprocessor.

24. The instrument of claim 21 wherein said parameters of said transmission line processor comprise a length of said transmission line, a characteristic impedance of said transmission line and a complex phase velocity factor of said transmission line.

25. The instrument of claim 21 wherein said shunt electrical quantities are computed from a grid-to-ground gap length, an area of said wafer, a grid-to-ground dielectric constant and a grid-to-ground conductive loss component.

26. The instrument of claim 25 wherein said grid-to-ground transformation unit comprises a memory storing said shunt electrical quantities.

27. The instrument of claim 26 wherein said grid-to-ground transformation unit further comprises a processor for computing said shunt electrical quantities.

28. The instrument of claim 21 wherein said load electrical quantities are computed from a grid-to-wafer gap thickness, an area of said wafer, a grid-to-wafer dielectric constant and a grid-to-wafer conductive loss component.

29. The instrument of claim 28 wherein said grid-to-wafer transformation unit comprises a memory storing said load electrical quantities.

30. The instrument of claim 29 wherein said grid-to-wafer transformation unit further comprises a processor for computing said load electrical quantities.

31. The instrument of claim 21 wherein said combined transformation processor computes said wafer voltage and an imaginary part of said plasma admittance comprising a plasma susceptance, and computes at least one of said ion density and etch rate from said wafer voltage and said plasma susceptance.

32. The reactor of claim 15 further comprising:

a memory storing sets of contours of constant performance parameter values for one of bias power and source power as a function of the other, said sets of contours comprising at least one of a set of contours of constant wafer voltage, a set of contours of constant ion density, a set of contours of constant etch rate;

a process set point controller capable of accepting user-defined target values for control parameters comprising at least one of wafer voltage, ion density and etch rate and for finding a value pair of source power and bias power at which the corresponding ones of said contours of constant performance parameter values intersect; and

said process set point controller having an output at which said value pair of source power and bias power are coupled as power level commands to said plasma RF source power supply and said plasma RF bias power supply, respectively.

33. The plasma reactor of claim 32 wherein said sets of contours comprise different sets of said contours for different chamber pressures.

34. The plasma reactor of claim 32 wherein said sets of contours comprise different sets of contours for different values of a control parameter.

36. The plasma reactor of claim 32 wherein said sets of contours comprise different sets of said contours for different chamber pressures.

37. The plasma reactor of claim 32 wherein said sets of contours comprise different sets of contours for different values of a control parameter.

35. A plasma reactor comprising:

a vacuum chamber and a wafer support pedestal within said chamber for supporting a wafer to be processed within said chamber;

a process gas inlet for furnishing process gases into said chamber;

an overhead RF power applicator near a ceiling of said chamber and overlying said wafer support pedestal, a plasma RF source power supply and a first impedance match circuit connected between said plasma RF source power supply and said overhead electrode;

a plasma RF bias power supply and a second impedance match circuit connected between said plasma RF bias power supply and said wafer support pedestal;

a memory storing sets of contours of constant performance parameter values for one of bias power and source power as a function of the other, said sets of contours comprising at least one of a set of contours of constant wafer voltage, a set of contours of constant ion density, a set of contours of constant etch rate;

a process set point controller capable of accepting user-defined target values for control parameters comprising at least one of wafer voltage, ion density and etch rate and for finding a value pair of source power and bias power at which the corresponding ones of said contours of constant performance parameter values intersect; and

said process set point controller having an output at which said value pair of source power and bias power are coupled as power level commands to said plasma RF source power supply and said plasma RF bias power supply, respectively.

38. The plasma reactor of claim 35 wherein said second impedance match circuit comprises sensor circuits providing measurement signals representing bias power, voltage and current at said impedance match circuit, said reactor further comprising:

a measurement instrument for converting said measurement signals representing bias power, voltage and current at said impedance match circuit into at least one of a wafer voltage measurement signal representing the voltage on a wafer supported on said wafer pedestal, an ion density measurement signal representing plasma ion density in said chamber and an etch rate measurement signal representing etch rate on said wafer; and

a constant contour generator for slewing the power levels of said plasma RF bias power generator and said plasma RF source power generator and correlating resulting changes in at least one of said wafer voltage measurement signal, ion density measurement signal and said etch rate measurement signal so as to produce said contours of constant performance parameter values.