III-Phosphide and III-Arsenide flip chip light-emitting devices

• US 20040227148A1
• Filed: 06/14/2004
• Published: 11/18/2004
• Est. Priority Date: 06/03/1997
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds Lighting US LLC (Apollo Global Management, Inc.)
• Inventors: Krames, Michael R., Martin, Paul S., Steranka, Frank M., Camras, Michael D., Steigerwald, Daniel A., Stockman, Stephen A., Ludowise, Michael J., Kish, Fred A.
• Granted Patent: US 6,946,309 B2
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 33/02 : characterised by the semiconductor bodies
• CPC Class Codes: H01L 33/08 : with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/14 : with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/20 : with a particular shape, e.g. curved or truncated substrate

Abstract

A light-emitting semiconductor device includes a stack of layers including an active region. The active region includes a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof. A superstrate substantially transparent to light emitted by the active region is disposed on a first side of the stack. First and second electrical contacts electrically coupled to apply a voltage across the active region are disposed on a second side of the stack opposite to the first side. In some embodiments, a larger fraction of light emitted by the active region exits the stack through the first side than through the second side. Consequently, the light-emitting semiconductor device may be advantageously mounted as a flip chip to a submount, for example.

Claims

1-36. -36. (Canceled).

37. A method of forming a light-emitting semiconductor device, said method comprising:

forming a structure including a stack of semiconductor layers overlying a host substrate, said stack including an active region, said active region comprising a semiconductor selected from the group consisting of III-Phosphides, III-Arsenides, and alloys thereof,

attaching a superstrate to a first side of said structure, said superstrate substantially transparent to light emitted by said active region;

removing at least a portion of said host substrate; and

forming a first electrical contact and a second electrical contact on a second side of said structure opposite to said first side, said first electrical contact and said second electrical contact electrically coupled to apply a voltage across said active region.

38. The method of claim 37, further comprising bonding said superstrate to said stack.

39. The method of claim 37, further comprising growing said superstrate on said stack.

40. The method of claim 37, wherein the act of removing said portion of said host substrate precedes the act of attaching said superstrate to said structure.

41. The method of claim 37, wherein the act of attaching said superstrate to said structure precedes the act of removing said portion of said host substrate.