Reference current generator, and method of programming, adjusting and/or operating same

• US 20040227166A1
• Filed: 05/07/2004
• Published: 11/18/2004
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Ecole polytechnique fãdãrale de lausanne epfl (Schweizerische Eidgenossenschaft)
• Inventors: Declercq, Michel, Kayal, Maher, Pastre, Marc, Portmann, Lionel, Blagojevic, Marija
• Granted Patent: US 6,912,150 B2
• Time in Patent Office: Days
• US Class Current: 257/222
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

Claims

1. A semiconductor dynamic random access memory device comprising:

a plurality of bit lines, including a first bit line and a second bit line;

a sense amplifier, having a first input coupled to the first bit line and a second input coupled to the second bit line;

a first digitally controlled reference current generator, selectively coupled to the first bit line, to generate a first reference current in response to a first reference current control word;

a plurality of memory cells, including a first memory cell coupled to the first bit line and a second memory cell coupled to the second bit line, to store a first data state and a second data state, each memory cell includes;

at least one transistor including a source region, a drain region, a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating, and a gate spaced apart from, and capacitively coupled to, the body region;

wherein the transistor includes a first state which is representative of a first charge in the body region and a second state which is representative of a second charge in the body region, and

wherein the memory cell is in;

(1) the first data state when the first transistor is in the first state and (2) the second data state when the first transistor is in the second state; and

wherein the sense amplifier uses the first reference current to sense whether the second memory cell is in the first data state or the second data state.

2. The semiconductor dynamic random access memory device of claim 1 further including a second digitally controlled reference current generator, selectively coupled to the second bit line, to generate a second reference current in response to a second reference current control word wherein the sense amplifier uses the second reference current to sense whether the first memory cell is in the first data state or the second data state.

3. The semiconductor dynamic random access memory device of claim 1 wherein the first digitally controlled reference current generator is selectively coupled to the second bit line when the sense amplifier is sensing the data state of the first memory cell, and wherein the sense amplifier uses the first reference current to sense whether the first memory cell is in the first data state or the second data state.

4. The semiconductor dynamic random access memory device of claim 1 further including a control unit, coupled to the first digitally controlled reference current generator, to generate the reference current control word.

5. The semiconductor dynamic random access memory device of claim 4 wherein the control unit uses a successive approximation technique to determine the reference current control word.

6. The semiconductor dynamic random access memory device of claim 5 wherein the control unit is selectively coupled to the sense amplifier to execute the successive approximation technique that determines the reference current control word.

7. The semiconductor dynamic random access memory device of claim 1 further including:

a second digitally controlled reference current generator, coupled to the second bit line, to generate a second reference current in response to a second reference current control word wherein the sense amplifier uses the second reference current to sense whether the first memory cell is in the first data state or the second data state; and

a control unit, coupled to the first and second digitally controlled reference current generators, to generate the first reference current control word and the second reference current control word.

8. The semiconductor dynamic random access memory device of claim 1 further including a control unit to generate the first reference current control word during an initialization sequence of the memory device.

9. The semiconductor dynamic random access memory device of claim 1 further including a control unit to generate the first reference current control word during normal operation of the memory device.

10. The semiconductor dynamic random access memory device of claim 1 further including a second digitally controlled reference current generator, coupled to the second bit line, to generate a reference current in response to the first reference current control word wherein the sense amplifier uses the reference current to sense whether the first memory cell is in the first data state or the second data state.

11. The semiconductor dynamic random access memory device of claim 1 wherein the first and second bit lines are connected to the sense amplifier in an open bit line architecture.

12. The semiconductor dynamic random access memory device of claim 1 wherein the first and second bit lines are connected to the sense amplifier in a folded bit line architecture.

19. The semiconductor dynamic random access memory device of claim 1 further including a control unit to generate the reference current control words during normal operation of the memory device, and wherein the reference current control words are provided to the reference current generators during normal operation.

13. A semiconductor dynamic random access memory device comprising:

a plurality of memory cells arranged in a matrix of rows and columns, each memory cell includes;

at least one transistor including a source region, a drain region, a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating, and a gate spaced apart from, and capacitively coupled to, the body region;

wherein the transistor includes a first state which is representative of a first charge in the body region and a second state which is representative of a second charge in the body region, and wherein the memory cell is in;

(1) the first data state when the first transistor is in the first state and (2) the second data state when the first transistor is in the second state; and

a plurality of bit lines, including a first bit line connected to a first memory cell and a second bit line connected to a second memory cell;

a plurality of digitally controlled reference current generators, each digitally controlled reference current generator being selectively coupled to an associated one of the bit lines to provide a reference current in response to an associated reference current control word; and

a plurality of sense amplifiers, each sense amplifier having a first input coupled to first associated bit line and a second input coupled to a second associated bit line wherein each sense amplifier senses;

(1) the data state of the memory cells connected to the first associated bit line using the reference current provided by a digitally controlled reference current generator connected to the second associated bit line, and (2) the data state of the memory cells connected to the second associated bit line using the reference current provided by a digitally controlled reference current generator connected to the first associated bit line.

14. The semiconductor dynamic random access memory device of claim 13 further including a control unit, coupled to the first digitally controlled reference current generator, to generate the associated reference current control word for each reference current generator.

15. The semiconductor dynamic random access memory device of claim 14 wherein the control unit uses a successive approximation technique to determine the reference current control word for at least one reference current generator.

16. The semiconductor dynamic random access memory device of claim 15 wherein the control unit is selectively coupled to the sense amplifier associated with the at least one reference current generator to execute the successive approximation technique that determines the reference current control word.

17. The semiconductor dynamic random access memory device of claim 13 wherein the reference current control words are provided to the reference current generators during an initialization sequence.

18. The semiconductor dynamic random access memory device of claim 13 wherein the reference current control words are provided to the reference current generators during normal operation.

20. The semiconductor dynamic random access memory device of claim 13 wherein the bit line layout is an open bit line architecture.

21. The semiconductor dynamic random access memory device of claim 13 wherein the bit line layout is a folded bit line architecture.

22. A semiconductor dynamic random access memory device comprising:

a plurality of bit lines, including first and second bit lines;

a sense amplifier, having a first input coupled to the first bit line and a second input coupled to the second bit line;

a first reference current generator, selectively coupled to the first bit line, to generate a first reference current in response to a reference current control word;

a second reference current, selectively coupled to the second bit line, to generate a second reference current in response to the reference current control word;

a plurality of memory cells, including a first memory cell coupled to the first bit line and a second memory cell coupled to the second bit line, wherein the memory cells each store a first data state and a second data state, and wherein each memory cell includes;

at least one transistor including a source region, a drain region, a body region disposed between and adjacent to the source region and the drain region, wherein the body region is electrically floating, and a gate spaced apart from, and capacitively coupled to, the body region; and

wherein the transistor includes a first state which is representative of a first charge in the body region and a second state which is representative of a second charge in the body region;

wherein the memory cell is in;

(1) the first data state when the first transistor is in the first state and (2) the second data state when the first transistor is in the second state; and

wherein the sense amplifier uses;

(1) the first reference current to sense whether the second memory cell is in the first data state or the second data state and (2) the second reference current to sense whether the first memory cell is in the first data state or the second data state.

23. The semiconductor dynamic random access memory device of claim 22 further including a control unit, coupled to the first reference current generator, to adjust the first reference current generated by the first reference current generator.

24. The semiconductor dynamic random access memory device of claim 23 wherein the control unit uses a successive approximation technique to determine the reference current control word.

25. The semiconductor dynamic random access memory device of claim 24 wherein the control unit is selectively coupled to the sense amplifier to execute the successive approximation technique that determines the reference current control word.

26. The semiconductor dynamic random access memory device of claim 22 wherein the first and second reference current generators are digitally controlled reference current generators.

27. The semiconductor dynamic random access memory device of claim 22 further including a control unit to generate the first reference current control word during an initialization sequence of the memory device.

28. The semiconductor dynamic random access memory device of claim 22 further including a control unit to generate the first reference current control word during normal operation of the memory device.

29. The semiconductor dynamic random access memory device of claim 22 wherein the first and second reference current generators are analog reference current generators.

30. The semiconductor dynamic random access memory device of claim 22 wherein the layout of the first and second bit lines is an open bit line architecture.

31. The semiconductor dynamic random access memory device of claim 22 wherein the layout of the first and second bit lines is a folded bit line architecture.