Semiconductor devices and method for manufacturing the same

• US 20040227169A1
• Filed: 06/17/2004
• Published: 11/18/2004
• Est. Priority Date: 12/26/2000
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kawashima, Takahiro, Asai, Akira, Kubo, Minoru, Ichikawa, Yo
• Granted Patent: US 7,244,972 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

In a field effect transistor, an Si layer 11, an SiC (Si_1-yC_y) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.

Claims

1. A semiconductor device, comprising at least one field effect transistor, the field effect transistor including:

a first semiconductor layer;

a first active layer provided on the first semiconductor layer, an uppermost portion of the first active layer being a nitride-containing layer and a main portion of the first active layer being a second semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

<

1, x+y>

0); and

a gate electrode provided on the first active layer,

wherein the nitride-containing layer is made of at least one material selected from carbon nitride (CN), aluminum nitride (AIN) gallium nitride (GaN), germanium nitride (GeN), silicon carbon nitride (SiCN) and germanium carbon nitride (GeCN)

2. The semiconductor device of claim 1, wherein a distance between the nitride-containing layer and the second semiconductor layer in the first active layer is 2 nm or less.

3. The semiconductor device of claim 1, wherein at least an upper portion of the nitride-containing layer is oxidized.

4. The semiconductor device of claim 1, wherein:

the first semiconductor layer has a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1); and

the second semiconductor layer has a composition expressed as Si_1-yC_y (0<

y<

1).

5. The semiconductor device of claim 4, wherein the first semiconductor layer is under a tensile strain.

6. The semiconductor device of claim 4, wherein the second semiconductor layer is used as an n-channel through which electrons travel.

7. The semiconductor device of claim 4, wherein the second semiconductor layer is used as a p-channel through which holes travel.

8. The semiconductor device of claim 4, wherein:

the field effect transistor is an n-channel field effect transistor; and

the semiconductor device further comprises a p-channel field effect transistor, the p-channel field effect transistor including;

a third semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1);

a second active layer provided on the third semiconductor layer, an uppermost portion of the second active layer being a nitride-containing layer and a main portion of the second active layer being a fourth semiconductor layer having a composition expressed as Si_1-yC_y (O<

y<

1); and

a gate electrode provided on the second active layer.

9. The semiconductor device of claim 8, wherein:

the first semiconductor layer and the third semiconductor layer are formed from the same semiconductor film; and

the second semiconductor layer and the fourth semiconductor layer are formed from the same semiconductor film.

10. The semiconductor device of claim 1, wherein:

the first semiconductor layer has a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1); and

the second semiconductor layer has a composition expressed as Si_1-x-yGe_xC_y (0<

x<

1, 0<

y<

1).

11. The semiconductor device of claim 10, wherein the second semiconductor layer is used as an n-channel through which electrons travel.

12. The semiconductor device of claim 10, wherein the second semiconductor layer is used as a p-channel through which holes travel.

13. The semiconductor device of claim 10, wherein:

the field effect transistor is an n-channel field effect transistor; and

the semiconductor device further comprises a p-channel field effect transistor the p-channel field effect transistor including;

a fifth semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1,0≦

y<

1),

a third active layer provided on the fifth semiconductor layer, an uppermost portion of the third active layer being a nitride-containing layer and a main portion of the third active layer being a sixth semiconductor layer having a composition expressed as Si_1-yC_y (0<

y<

1); and

a gate electrode provided on the third active layer.

14. The semiconductor device of claim 13, wherein:

the first semiconductor layer and the fifth semiconductor layer are formed from the same film; and

the second semiconductor layer and the sixth semiconductor layer are formed from the same film.

15. The semiconductor device of claim 1, wherein:

the first semiconductor layer has a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1); and

the second semiconductor layer has a composition expressed as Si_1-xGe_x (0<

x<

1).

16. The semiconductor device of claim 15, wherein the second semiconductor layer is under a compressive strain.

17. The semiconductor device of claim 15, wherein the second semiconductor layer is used as an n-channel through which electrons travel.

18. The semiconductor device of claim 15, wherein the second semiconductor layer is used as a p-channel through which holes travel.

19. The semiconductor device of claim 15, wherein:

the field effect transistor is an n-channel field effect transistor; and

the semiconductor device further comprises a p-channel field effect transistor, the p-channel field effect transistor including;

a seventh semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1);

a fourth active layer provided on the seventh semiconductor layer, an uppermost portion of the fourth active layer being a nitride-containing layer and a main portion of the fourth active layer being an eighth semiconductor layer having a composition expressed as Si_1-xGe_x (0<

x<

1); and

a gate electrode provided on the fourth active layer.

20. The semiconductor device of claim 19, wherein:

the first semiconductor layer and the seventh semiconductor layer are formed from the same film; and

the second semiconductor layer and the eighth semiconductor layer are formed from the same film.

21. The semiconductor device of claim 1, wherein:

the first semiconductor layer is a lattice-relaxed layer having a composition expressed as Si_1-x-yGe_y (0<

x<

1, 0≦

y<

1);

the second semiconductor layer is a lattice-relaxed layer; and

the semiconductor device further comprises a tensile-strained ninth semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1) and provided between the first semiconductor layer and the second semiconductor layer in the first active layer.

22. The semiconductor device of claim 21, wherein the ninth semiconductor layer is used as an n-channel through which electrons travel.

23. The semiconductor device of claim 21, wherein the second semiconductor layer is used as a p-channel through which holes travel.

24. The semiconductor device of claim 21, further comprising a tenth semiconductor layer provided under the second semiconductor layer and having a graded composition expressed as Si_1-x-yGe_xC_y (0<

x<

1, 0<

y<

1) that is varied so that a crystal lattice dimension increases from a lower portion toward an upper portion.

25. The semiconductor device of claim 21, wherein:

the field effect transistor is an n-channel field effect transistor; and

the semiconductor device further comprises a p-channel field effect transistor, the p-channel field effect transistor including;

a lattice-relaxed tenth semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0<

x<

1, 0≦

y<

1);

a fifth active layer, an uppermost portion of the fifth active layer being a nitride-containing layer and a main portion of the fifth active layer including a lattice-relaxed eleventh semiconductor layer having the same composition as that of the tenth semiconductor layer and a tensile-strained twelfth semiconductor layer that is provided between the tenth semiconductor layer and the eleventh semiconductor layer and has a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1); and

a gate electrode provided on the fifth active layer.

26. The semiconductor device of claim 25, wherein:

the first semiconductor layer and the tenth semiconductor layer are formed from the same film;

the second semiconductor layer and the eleventh semiconductor layer are formed the same film; and

the ninth semiconductor layer and the twelfth semiconductor layer are formed from the same film.

27. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a substrate including a semiconductor layer, which is a first semiconductor layer;

(b) forming a second semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1, x+y>

0) on the first semiconductor layer;

(c) nitriding a surface portion of the second semiconductor layer so as to form a nitride-containing layer; and

(d) forming a gate electrode on the second semiconductor layer,

wherein the nitride-containing layer is made of at least one material selected from carbon nitride (CN), aluminum nitride (AIN), gallium nitride (GaN), germanium nitride (GeN), silicon carbon nitride (SiCN) and germanium carbon nitride (GeCN).

28. The method for manufacturing a semiconductor device of claim 27, wherein in the step (c), an ECR plasma is used.

29. A method for manufacturing a semiconductor device, comprising the steps of:

(a) preparing a substrate including a semiconductor layer, which is a first semiconductor layer;

(b) forming a second semiconductor layer having a composition expressed as Si_1-x-yGe_xC_y (0≦

x<

1, 0≦

y<

1, x+y>

0) on the first semiconductor layer;

(c) forming a nitride-containing layer by a CVD method on the second semiconductor layer; and

(d) forming a gate electrode on the second semiconductor layer,

wherein the nitride-containing layer is made of at least one material selected from carbon nitride (CN), aluminum nitride (AIN), gallium nitride (GaN), germanium nitride (GeN), silicon carbon nitride (SiCN) and germanium carbon nitride (GeCN).