Microelectronic assemblies having compliant layers

• US 20040227225A1
• Filed: 06/22/2004
• Published: 11/18/2004
• Est. Priority Date: 10/31/1995
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Karavakis, Konstantine, Fjelstad, Joseph
• Granted Patent: US 7,112,879 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/48624 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4951 : Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A microelectronic package includes a microelectronic element having contacts accessible at a surface thereof, a layer overlying the microelectronic element, the layer having a first surface and a sloping peripheral edge extending away from the first surface of the layer, and conductive terminals overlying the microelectronic element, wherein the layer supports the conductive terminals over the microelectronic element. The package also includes conductive traces having first ends electrically connected with the contacts of the microelectronic element and second ends electrically connected with the conductive terminals, with at least one of the conductive traces having a section that is in contact with and extends along the sloping peripheral edge of the layer, and a compliant material disposed between the conductive terminals and the microelectronic element so that the conductive terminals are movable relative to the microelectronic element.

Claims

1. A microelectronic package comprising:

a microelectronic element having contacts accessible at a surface thereof;

a layer overlying said microelectronic element, said layer having a first surface and a sloping peripheral edge extending away from the first surface of said layer;

conductive terminals overlying said microelectronic element, wherein said layer supports said conductive terminals over said microelectronic element;

conductive traces having first ends electrically connected with said contacts of said microelectronic element and second ends electrically connected with said conductive terminals, wherein at least one of said conductive traces has a section that is in contact with and extends along the sloping peripheral edge of said layer; and

a compliant material disposed between said conductive terminals and said microelectronic element so that said conductive terminals are movable relative to said microelectronic element.

2. The package as claimed in claim 1, wherein said contacts are provided in peripheral regions of said microelectronic element.

3. The package as claimed in claim 1, wherein said contacts face said layer.

4. The package as claimed in claim 1, wherein said microelectronic element is a semiconductor chip.

5. The package as claimed in claim 1, wherein said layer comprises an epoxy.

6. The package as claimed in claim 5, wherein said epoxy is compliant.

7. The package as claimed in claim 1, wherein said conductive traces are substantially longer than wide.

8. The package as claimed in claim 1, further comprising a dielectric layer overlying said conductive traces and the sloping peripheral edge of said layer, wherein said dielectric layer has openings for said terminals.

9. The package as claimed in claim 1, further comprising conductive masses disposed on said conductive terminals.

10. The package as claimed in claim 9, wherein said conductive masses comprise solder bumps.

11. The package as claimed in claim 1, wherein said compliant material supports said conductive terminals over said microelectronic element.

12. The package as claimed in claim 1, wherein said microelectronic element has a peripheral edge and the sloping peripheral edge of said layer is adjacent the peripheral edge of said microelectronic element.

13. A microelectronic package comprising:

a semiconductor chip having a plurality of peripheral chip contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;

a layer overlying said semiconductor chip, said layer having a first surface and a peripheral edge that extends from the first surface of said layer and toward said semiconductor chip;

conductive terminals overlying said layer and said semiconductor chip, wherein said layer supports said conductive terminals over said semiconductor chip and wherein the peripheral edge of said layer slopes away from said conductive terminals;

conductive traces having first ends electrically connected with said contacts of said semiconductor chip and second ends electrically connected with said conductive terminals, wherein at least one of said conductive traces has a section that extends along the sloping, peripheral edge of said layer; and

a compliant material disposed between said conductive terminals and said semiconductor chip so that said conductive terminals are movable relative to said semiconductor chip.

14. The package as claimed in claim 13, wherein at least one of said conductive traces has a second section that extends inwardly toward the central region of said semiconductor chip.

15. The package as claimed in claim 13, wherein said layer has openings formed therein for electrically interconnecting said conductive traces and said chip contacts.

16. The package as claimed in claim 13, wherein said layer comprises an epoxy.

17. The package as claimed in claim 16, wherein said epoxy is compliant.

18. The package as claimed in claim 13, further comprising a dielectric layer overlying said conductive traces and the sloping, peripheral edge of said layer, wherein said dielectric layer has openings for said conductive terminals.

19. The package as claimed in claim 13, further comprising conductive masses disposed on said conductive terminals.

20. The package as claimed in claim 13, wherein said compliant material supports said conductive terminals over said semiconductor chip.

21. The package as claimed in claim 13, wherein said traces are substantially longer than wide.

22. A microelectronic package comprising:

a wafer including a plurality of microelectronic elements, each said microelectronic element having contacts on a surface thereof;

a layer overlying at least one of said microelectronic elements, said layer having a first surface and a sloping peripheral edge extending away from the first surface of said layer;

conductive terminals overlying the at least one of said microelectronic elements, wherein said layer supports said conductive terminals over the at least one of said microelectronic elements;

conductive traces having first ends electrically connected with said contacts of the at least one of said microelectronic elements and second ends electrically connected with said conductive terminals, wherein at least one of said conductive traces has a section that extends along the sloping peripheral edge of said layer; and

a compliant material disposed between at least one of said conductive terminals and the at least one of said microelectronic elements so that the at least one of said conductive terminals is movable relative to the at least one of said microelectronic elements.

23. The package as claimed in claim 22, wherein said layer comprises epoxy.

24. A method of making a microelectronic package comprising:

providing a semiconductor chip having a plurality of peripheral contacts on a face surface thereof and a central region bounded by the peripheral chip contacts;

depositing an epoxy layer over said semiconductor chip, said epoxy layer having a first surface and a peripheral edge that slopes away from the first surface;

selectively forming bond ribbons over said epoxy layer so that said bond ribbons are in contact with and extend over the sloping, peripheral edge of said epoxy layer and said bond ribbons electrically connect said contacts to conductive terminals overlying said epoxy layer; and

providing a compliant material between said conductive terminals and said semiconductor chip.

25. The method as claimed in claim 24, further comprising providing a dielectric layer over said bond ribbons, said dielectric layer having openings for accessing said conductive terminals.

26. The method as claimed in claim 24, further comprising providing conductive masses on said conductive terminals for electrically interconnecting said package with another electrical component.

27. The method as claimed in claim 24, wherein said bond ribbons are substantially longer than wide.