Optimization of error loops in distributed power amplifiers

• US 20040227570A1
• Filed: 05/12/2003
• Published: 11/18/2004
• Est. Priority Date: 05/12/2003
• Status: Active Grant

• Current Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Original Assignee: Andrew Corporation (CommScope Holding Company, Inc.)
• Inventors: Jackson, Donald G., Hoppenstein, Russell J.
• Granted Patent: US 6,972,622 B2
• Time in Patent Office: Days
• US Class Current: 330/151
• CPC Class Codes: H03F 1/3229 using a loop for error extraction and another loop for error subtraction
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

Several feed-forward RF power amplifiers configured for use in a distributed array, each having a main amplifier within a carrier null loop and an error amplifier within an error loop. Each carrier null loop includes a switch configured to selectively disable the carrier null loop, thereby disabling the carrier null loop, and injecting an actual RF signal into the error loop allowing the error loop to be optimized using the actual RF signal.

Claims

1. An apparatus comprising:

a main amplifier within a carrier null loop;

an error amplifier within an error loop;

a switch disposed in the carrier null loop and configured to selectively disable the carrier null loop to provide injection of an actual RF signal into the error loop to allow optimization of the error loop using the actual RF signal.

2. The apparatus of claim 1, further comprising a power splitter disposed in the carrier null loop and coupled intermediate the switch and the main amplifier and configured to divide an RF input signal.

3. The apparatus of claim 2, further comprising a coupler disposed in the carrier null loop and coupled to the main amplifier and configured to sample the output of the main amplifier.

4. The apparatus of claim 3, further comprising an attenuator disposed in the carrier null loop and coupled to the coupler and configured to select the level of the sampled output of the main amplifier.

5. The apparatus of claim 4, further comprising a first combiner disposed in the carrier null loop and coupled to the attenuator and the switch and configured to substantially cancel the input signal carrier during normal operation resulting in primarily IMD products being coupled to the error amplifier.

6. The apparatus of claim 5, wherein the error amplifier is coupled to the first combiner.

7. The apparatus of claim 6, further comprising a second combiner disposed in the error loop and coupled to the coupler and the error amplifier and configured to combine IMD products generated by the main amplifier and IMD products manipulated in the error loop, thereby producing an output signal with acceptable IMD.

8. The apparatus of claim 7, further comprising a power detector coupled to the second combiner and configured to be read by a processor.

9. The apparatus of claim 1, further comprising a processor, the switch controlled by the processor.

10. The apparatus of claim 9, further comprising an attenuator, the attenuator configured to reduce the level of the actual RF signal injected into the error loop, the attenuator also controlled by the processor.

11. The apparatus of claim 9, further comprising a power detector coupled to the error amplifier and configured to be read by the processor.

12. An amplifier system, the system comprising:

an array of amplifiers, with each such amplifier comprising;

a main amplifier within a carrier null loop;

an error amplifier within an error loop;

a switch disposed in the carrier null loop and configured to selectively disable the carrier null loop to provide injection of an actual RF signal into the error loop to allow optimization of the error loop using the actual RF signal.

13. The amplifier system of claim 12, wherein each amplifier further comprises a power splitter disposed in the carrier null loop and coupled to the switch and the main amplifier and configured to divide an RF input signal.

14. The amplifier system of claim 13, wherein each amplifier further comprises a coupler disposed in the carrier null loop and coupled to the main amplifier and configured to sample the output signal of the main amplifier.

15. The amplifier system of claim 14, wherein each amplifier further comprises an attenuator disposed in the carrier null loop and coupled to the coupler and configured to select the level of the sampled output signal.

16. The amplifier system of claim 15, wherein each amplifier further comprises a first combiner disposed in the carrier null loop and coupled to the attenuator and the switch and configured to substantially cancel the input signal carrier during normal operation resulting in primarily IMD products being coupled to the error amplifier.

17. The amplifier system of claim 16, wherein the error amplifier is coupled to the first combiner in each amplifier.

18. The amplifier system of claim 17, wherein each amplifier further comprises a second combiner disposed in the error loop and coupled to the coupler and the error amplifier and configured to combine IMD products generated by the main amplifier and IMD products manipulated in the error loop, thereby producing an output signal with acceptable IMD.

19. The amplifier system of claim 18, wherein each amplifier further comprises a power detector coupled to the second combiner and configured to be read by a processor.

20. The amplifier system of claim 12, further comprising a processor, the switch within each amplifier controlled by the processor.

21. The amplifier system of claim 20, wherein each amplifier further comprises an attenuator, the attenuator configured to reduce the level of the actual RF signal injected into the error loop, the attenuator also controlled by the processor.

22. The amplifier system of claim 20, wherein each amplifier further comprises a power detector coupled to the error amplifier and configured to be read by the processor.

23. A method of optimizing an error loop in an amplifier having a carrier null loop, the method comprising:

selectively disabling the carrier null loop; and

,

performing corrections in the error control loop while the carrier null loop is disabled.

24. The method of claim 23, wherein the carrier null loop is selectively disabled using a switch.

25. The method of claim 23, wherein performing corrections in the error control loop while the carrier null loop is disabled includes using an actual RF signal to perform corrections.

26. The method of claim 23, further comprising reducing input signal power.

27. The method of claim 23, further comprising adjusting input signal power to achieve substantially the same input signal power in the error loop as is present during normal operation.

28. The method of claim 23, further comprising adjusting at least one of the error loop amplitude and phase to minimize power at the amplifier output.

29. The method of claim 23, further comprising selectively enabling the carrier null loop after adjusting at least one of the error loop amplitude and phase to minimize power at the amplifier output.

30. The method of claim 23, further comprising restoring the input signal power after selectively enabling the carrier null loop and adjusting at least one of the error loop amplitude and phase to minimize power at the amplifier output.

31. A method of optimizing an array comprised of amplifiers, with each amplifier having an error loop and a carrier null loop, the method comprising:

disabling at least one amplifier from the array while at least one other amplifier in the array continues amplifying an actual RF signal, including disabling the carrier null loop of the disabled amplifier, and

performing corrections in the error loop of the disabled amplifier while the carrier null loop is disabled and while the other amplifier in the array continues amplifying the actual RF signal.

32. The method of claim 31, wherein the carrier null loop is disabled using a switch.

33. The method of claim 31, wherein performing corrections in the error control loop of the disabled amplifier while the carrier null loop is disabled includes using the actual RF signal to perform corrections.

34. The method of claim 31, further comprising reducing input signal power to the disabled amplifier.

35. The method of claim 31, further comprising adjusting input signal power of the disabled amplifier to achieve substantially the same input signal power in the error loop as is present during normal operation.

36. The method of claim 31, further comprising adjusting at least one of the error loop amplitude and phase to minimize power at the disabled amplifier output.

37. The method of claim 31, further comprising enabling the carrier null loop after adjusting at least one of the error loop amplitude and phase to minimize power at the disabled amplifier output.

38. The method of claim 31, further comprising restoring the input signal power after selectively enabling the carrier null loop and adjusting at least one of the error loop amplitude and phase to minimize power at the amplifier output.

39. The method of claim 31, further comprising, after performing corrections in the error control loop of the disabled amplifier, sequentially disabling each other amplifier in the array and performing corrections on the error control loops thereof while continuing to amplify the actual RF signal.