Shift register
First Claim
1. A shift register, comprising a plurality of stages connected in cascade for shifting input signals in accordance with a plurality of phase-delayed control signals, a first supply voltage, and a second supply voltage, and for applying the shifted input signals as output signals and as input signals of the succeeding ones of stages, wherein each of plurality of stages comprises:
- a first controller for selectively applying an input signal and a first supply voltage to a first node arranged between first to third transistors that form a conductive path between a supply line of the input signal and an input line of the first supply voltage;
a second controller for selectively applying the first supply voltage and the second supply voltage to a second node arranged between fourth and fifth transistors forming a conductive path between an input line of the second supply voltage and the input line of the first supply voltage; and
an output buffer for selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line sixth and seventh transistors forming a conductive path between the input line of the first supply voltage and an input line of the predetermined control signal, wherein, when the fourth transistor is turned off and when the fifth transistor is turned on, the fifth transistor sustains a voltage present at the second node equal to the first supply voltage if the fourth transistor is turned off.
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Accused Products
Abstract
A shift register includes stages shifting an input signal with phase-delayed control signals and first and second supply voltages, and for applying shifted input signals as output signals and as input signals of succeeding stages. Each of the stages includes a first controller selectively applying an input signal and a first supply voltage to a first node between first to third transistors; a second controller selectively applying the first and second supply voltages to a second node between fourth and fifth transistors; and an output buffer selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line between sixth and seventh transistors, wherein the fifth transistor may be turned on to sustain a voltage present at the second node equal to the first supply voltage when the fourth transistor is turned off.
66 Citations
21 Claims
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1. A shift register, comprising a plurality of stages connected in cascade for shifting input signals in accordance with a plurality of phase-delayed control signals, a first supply voltage, and a second supply voltage, and for applying the shifted input signals as output signals and as input signals of the succeeding ones of stages, wherein each of plurality of stages comprises:
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a first controller for selectively applying an input signal and a first supply voltage to a first node arranged between first to third transistors that form a conductive path between a supply line of the input signal and an input line of the first supply voltage;
a second controller for selectively applying the first supply voltage and the second supply voltage to a second node arranged between fourth and fifth transistors forming a conductive path between an input line of the second supply voltage and the input line of the first supply voltage; and
an output buffer for selectively applying a predetermined control signal and the first supply voltage as an output signal to a stage output line sixth and seventh transistors forming a conductive path between the input line of the first supply voltage and an input line of the predetermined control signal, wherein, when the fourth transistor is turned off and when the fifth transistor is turned on, the fifth transistor sustains a voltage present at the second node equal to the first supply voltage if the fourth transistor is turned off. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification