Capacitor cell, semiconductor device and process for manufacturing the same

• US 20040228066A1
• Filed: 05/14/2004
• Published: 11/18/2004
• Est. Priority Date: 05/16/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kato, Toshikazu, Sakurabayashi, Taro
• Granted Patent: US 7,161,792 B2
• Time in Patent Office: Days
• US Class Current: 361/302
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0805 Capacitors only

Abstract

A capacitor cell for reducing noise in a high drive cell comprises a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.

Claims

1. A capacitor cell comprising:

at least one capacitor element for assisting in supplying power;

at least one path for mitigating the resistance of a power supply path, said one path being provided at an area positioned on an upper layer over said capacitor element and corresponding to an area where said capacitor cell is placed.

2. The capacitor cell as defined in claim 1, wherein said path for mitigating the resistance of said power supply path comprises

a via for connecting electrically a power supply line arranged on an interconnection layer over an area where said capacitor element is disposed to the power supply line provided on another interconnection layer which is located over said interconnection layer.

3. The capacitor cell as defined in claim 1, further comprising:

at least one power supply line arranged on one interconnection layer over said capacitor cell and disposed at an area corresponding to an area where said capacitor cell is placed; and

at least one via for electrically connecting said power supply line on said one interconnection layer to a power supply line provided on another interconnection layer different from said one interconnection layer corresponding to said power supply line on said one interconnection layer;

wherein said capacitor element constitutes a decoupling capacitor of a cell disposed adjacent to said capacitor cell and including one or plurality of active elements, and

wherein said power supply line provided on said one interconnection layer constitutes a power supply path to said cell.

4. The capacitor cell as defined in claim 1, wherein said capacitor element comprises a MOS gate capacitor.

5. The capacitor cell as defined in claim 1, wherein said capacitor element comprises:

a P-channel MOS transistor having a source connected to a higher voltage power supply; and

an N-channel MOS transistor having a source connected to a lower voltage power supply, a drain and gate connected to the gate and drain of said P-channel MOS transistor, respectively.

6. A semiconductor device including a capacitor cell as set forth in claim 1, wherein a power supply path in a power supply interconnection structure in said semiconductor device is additionally provided by said path of said capacitor cell.

7. A semiconductor device comprising:

a capacitor cell formed on said semiconductor substrate, including at least one capacitor element;

one interconnection layer positioned over said capacitor cell;

at least one other interconnection layer different from said one interconnection layer, on which a power supply line is provided;

at least one power supply line disposed on said one interconnection layer at an area corresponding to the area at which said capacitor cell is placed, said power supply line being electrically connected to corresponding said power supply line on said other interconnection layer through at least one connecting via; and

a cell disposed in the vicinity of said capacitor cell having a circuit including at least one active element;

wherein said capacitor cell constitutes a decoupling capacitor of said cell disposed in the vicinity of said capacitor cell; and

wherein said power supply line provided on said one interconnection layer at an area corresponding to the area where said capacitor cell is disposed constitutes a power supply path to said cell.

8. The semiconductor device as defined in claim 7, wherein said capacitor cell is placed on a row adjacent to one or both of the rows on which said cell is disposed.

9. The semiconductor device as defined in claim 7, wherein said capacitor cell is placed on one or both sides of adjacent column on which said cell is disposed on the same row as the row on which said cell is disposed.

10. The semiconductor device as defined in claim 7, wherein said cell has at least one power supply terminal on at least one side of a row on which said cell is disposed;

wherein said capacitor cell is provided in a correspondence with one side of said row on which said cell is disposed; and

wherein in said capacitor cell, said power supply line on of said one interconnection layer provided at an area corresponding to the area where said capacitor cell is placed, is electrically connected to said power supply terminal on one side of said row on which said cell is disposed.

11. The semiconductor device as defined in claim 7, wherein said cell comprises

at least one higher voltage power supply terminal and at least one lower voltage power supply terminal on each of both sides of a row on which said cell is disposed;

wherein said capacitor cell is provided on each of two rows sandwiching said row on which said cell is disposed;

wherein in one of said two capacitor cells, said power supply line on of said one interconnection layer, provided at an area corresponding to the area at which said one capacitor cell is placed, is electrically connected to said higher voltage power supply terminal; and

wherein in said other capacitor cell, said power supply line on of said one interconnection layer, provided at an area corresponding to the area at which said other capacitor cell is placed, is electrically connected to said higher voltage power supply terminal.

12. The semiconductor device as defined in claim 7, wherein said cell comprises at least one higher voltage power supply terminal and at least one lower voltage power supply terminal on both side of a row on which said cell is disposed;

wherein said semiconductor device has said capacitor cell on at least one of two columns sandwiching said capacitor cell therebetween on the same row as that on which said cell is disposed; and

wherein power is supplied to said higher and/or lower voltage power supply terminal of said cell through said power supply line provided on said one interconnection layer over said capacitor cell disposed area and is connected to higher and/or lower voltage power supply line of said other interconnection layer.

13. The semiconductor device as defined in claim 7, wherein said cell comprises a plurality of circuits arranged in parallel along a row on which said cell is disposed;

and

wherein power is supplied to said higher and lower voltage power supply terminals of said plurality of circuits through said power supply line provided on said one interconnection layer over said capacitor cell disposed area and is connected to higher and lower voltage power supply lines of said other interconnection layer.

14. The semiconductor device as defined in claim 7, wherein said one interconnection layer comprises a first and second power supply lines for the higher and lower power supplies respectively as power supply interconnection pattern provided at an area corresponding to the area where said capacitor cell is placed;

wherein said first and second power supply lines are electrically connected to corresponding two terminals of said capacitor element through at least one connecting via; and

wherein said one interconnection layer further comprises one or a plurality of third higher voltage power supply lines connected to higher voltage power supply line disposed on said other interconnection layer through at least one connecting via.

15. The semiconductor device as defined in claim 7, wherein said one interconnection layer comprises a first and second power supply lines for the higher and lower power supplies respectively as a power supply interconnection pattern provided at an area corresponding to the area where said capacitor cell is disposed;

wherein said first and second power supply lines are electrically connected to corresponding two terminals of said capacitor element through at least one connecting via; and

wherein said one interconnection layer further comprises one or a plurality of fourth lower voltage power supply lines connected to lower voltage power supply line provided on said other interconnection layer through at least one connecting via.

16. The semiconductor device as defined in claim 7, wherein said one interconnection layer comprises a first and second power supply lines for the higher and lower power supplies respectively as a power supply interconnection pattern provided at an area corresponding to the area where said capacitor cell is disposed;

wherein said first and second power supply lines are electrically connected to corresponding two terminals of said capacitor element through at least one connecting via;

wherein said one interconnection layer further comprises one or a plurality of third higher voltage power supply line connected to higher voltage power supply line provided on said other interconnection layer through at least one connecting via; and

wherein said one interconnection layer further comprises one or a plurality of fourth lower voltage power supply line connected to lower voltage power supply line provided on said other interconnection layer through at least one connecting via.

17. The semiconductor device as defined in claim 14, wherein said first and third power supply lines are placed in parallel to each other and extend in a direction of a row on which said capacitor cell is placed;

wherein there is provided as said power supply interconnection pattern, at least one fifth power supply line for connecting said first and third power supply lines to each other; and

wherein said second power supply line is not connected to said first and third power supply lines.

18. The semiconductor device as defined in claim 15, wherein said second and fourth power supply lines are placed in parallel to each other and extend in a direction of a row on which said capacitor cell is placed;

wherein there is provided as said power supply interconnection pattern, at least one sixth power supply line for connecting said second and fourth power supply lines to each other; and

wherein said first power supply line is not connected to said second and fourth power supply lines.

19. The semiconductor device as defined in claim 16, wherein said first to fourth power supply lines are placed in parallel to each other and extend in a direction of a row on which said capacitor cell is placed;

wherein there is provided as said power supply interconnection pattern, at least one fifth power supply line for connecting said first and third power supply lines to each other;

wherein there is provided as said power supply interconnection pattern, at least one sixth power supply line which connects said second and fourth power supply lines to each other; and

wherein said second and fourth power supply lines are not connected to said first and third power supply lines.

20. The semiconductor device as defined in claim 14, wherein said first and third power supply lines are electrically connected to a higher voltage power supply terminal of said cell which is adjacent to said capacitor cell.

21. The semiconductor device as defined in claim 15, wherein said second and fourth power supply lines are electrically connected to a lower voltage power supply terminal of said cell which is adjacent to said capacitor cell.

22. The semiconductor device as defined in claim 7, wherein said cell is a cell including a circuit having a relatively high driving capability (referred to as “

high drive cell”

); and

wherein said capacitor cell is placed on said high drive cell.

23. The semiconductor device as defined in claim 7, wherein said capacitor element comprises a MOS gate capacitor.

24. The semiconductor device as defined in claim 7, wherein said capacitor element comprises:

a P-channel MOS transistor having a source connected to a higher voltage power supply; and

an N-channel MOS transistor having a source connected to a lower voltage power supply, a drain and gate connected to a gate and drain of said PMOS transistor, respectively.

25. A method of designing a semiconductor device in which laying out of said semiconductor device is carried out by using a computer, said method comprising the steps of:

disposing at least one capacitor element; and

providing at least one path for mitigating the resistance of a power supply path at an area, said area provided on an upper layer over said capacitor element and corresponding to an area where said capacitor element is placed.

26. A method of designing a semiconductor device in which laying out of a cell based semiconductor device is carried out by using a computer, comprising the steps of:

registering as a macrocell in a cell library, a capacitor cell including at least one capacitor element, said capacitor cell comprising at least one path for mitigating the resistance of a power supply path (referred to as “

capacitor cell with a resistance mitigating path) at are area positioned on an upper layer over said capacitor element and corresponding to an area where said capacitor cell is placed;

reading information on circuit connection from a storage device in which circuit connection information is stored; and

disposing said capacitor cell with a resistance mitigating path registered in said cell library in a row or column adjacent to said cell as a capacitor cell assisting in supplying power to said cell, if the cell to be placed in accordance with said circuit connecting information has a relatively higher driving capability.

27. A method of manufacturing a semiconductor device, said method comprising the steps of:

forming at least one capacitor element for assisting in supplying power supply on a semiconductor substrate; and

providing at least one path for mitigating the resistance of a power supply path at an area positioned on an interconnection layer over said capacitor element and corresponding to an area where said capacitor cell is placed.