Method and device for generating a system clock
1 Assignment
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Accused Products
Abstract
A method and a device are presented for generating a system clock (OC) of a transmitting and/or receiving device with the aid of a system oscillator (1, 2). At least one control signal (PS, FS, JS, IS) is thereby evaluated by an evaluation unit (12) and the system oscillator (1, 11) is actuated as a function of this control signal (PS, FS, JS, IS) in order to change its frequency. This makes it possible for problems which arise due to an excessive frequency tolerance of an oscillating quartz element (1) to be eliminated or avoided by preventive means.
14 Citations
69 Claims
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1-35. -35. (canceled)
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36. A communications device comprising:
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an oscillator with a controllable output frequency;
a phase locked loop operably connected to receive the controllable output frequency of the oscillator, the phase locked loop generating a clock output based upon the controllable output frequency and generating at least one condition signal output indicative of a condition within the phase locked loop; and
an evaluation unit operably connected to the phase locked loop to receive the at least one condition signal and operably connected to the oscillator to control the output frequency of the oscillator based upon the at least one condition signal. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A communications device comprising:
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an oscillator with an output frequency;
a variable capacitance comprising at least one capacitor configured to be operably connected to the oscillator such that when the capacitance operably connected to the oscillator changes the output frequency of the oscillator; and
an evaluation unit operably configured to evaluate a signal indicative of at least one condition within the communications device, and operably connected to the variable capacitance to control variation of the capacitance based upon the at least one condition within the communications device. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. A method of generating a clock signal in a communications device having an oscillator, a phase locked loop, a digital signal processor and an evaluation unit, comprising the steps of:
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generating with the oscillator a generated output frequency;
generating with the phase locked loop a first clock using the first generated output frequency;
generating a control signal based upon the condition of at least one part within the device, wherein the part is selected from the group consisting of phase locked loop parts and the digital signal processor;
evaluating with the evaluation unit the control signal against a predetermined control signal value; and
controlling the oscillator to change the output frequency generated by the oscillator based upon the evaluation. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. A method of controlling the frequency of an oscillator within a communications device having a plurality of switchable capacitors providing a variable capacitance affecting the frequency of the oscillator, and a digital signal processor using at least one algorithm to process a signal detected by the communications device, the method comprising the steps of:
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outputting with the oscillator an output frequency;
modifying the operation of the processor based upon the at least one algorithm;
generating an efficacy signal indicative of the efficacy of the algorithm in modifying the operation of the processor; and
evaluating the efficacy signal, the method further comprising at least one of the steps of;
switching in capacitors to increase the capacitance; and
switching out capacitors to decrease the capacitance
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Specification