Variable gain amplifier circuit and gain control method thereof

• US 20040229586A1
• Filed: 03/02/2004
• Published: 11/18/2004
• Est. Priority Date: 04/14/2003
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Oshima, Takashi, Doi, Takeshi, Kyu, Irei, Maio, Kenji
• Granted Patent: US 7,005,922 B2
• Time in Patent Office: Days
• US Class Current: 455/240.1
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages

Abstract

In order to rapidly control the gains of a plurality of variable gain amplifiers VGAs, each of gain control circuits is configured to determine a gain to be set therein, based on gain control information received from other gain control circuits existing in its preceding stage or stages and the signal level detected by a level detector circuit connected thereto. By carrying out such gain control, a total application gain is stabilized more quickly by gain control. Therefore, even in receiving systems that the preparation period for reception is very short, desired gain control is achieved within this period and stable data reception can be performed.

Claims

1. A variable gain amplifier circuit comprising:

a plurality of variable gain circuits;

a plurality of level detector circuits which detect signal levels at respective inputs of said plurality of variable gain circuits; and

a plurality of gain control circuits which separately control respective gains of said plurality of variable gain circuits,

wherein each of said plurality of gain control circuits determines a gain to be set therein, based on the signal level detected by one which is connected thereto of said plurality of level detector circuits and information about gain control received from a part or all of other gain control circuits existing in its preceding stage or stages.

2. The variable gain amplifier circuit according to claim 1,

wherein said plurality of level detector circuits are connected to said plurality of variable gain circuits, respectively, and

wherein said plurality of gain control circuits are connected to said plurality of level detector circuits, respectively.

3. The variable gain amplifier circuit according to claim 1, further comprising:

a plurality of filters separately connected to respective outputs of said plurality of variable gain amplifiers; and

a filtered attenuation evaluating circuit which evaluates the quantity of signal attenuation by said plurality of filters, based on the signal levels detected by said plurality of level detector circuits,

wherein each of said gain control circuits controls the gain of one which is connected thereto of said variable gain amplifiers, based on signal attenuation evaluated by said filtered attenuation evaluating circuit and the signal level detected and output by one which is connected thereto of said plurality of level detector circuits.

4. The variable gain amplifier circuit according to claim 1, further comprising:

a plurality of filters separately connected to respective outputs of said plurality of variable gain amplifiers;

an interference attenuation evaluating circuit which evaluates the quantity of attenuation of interference signals, based on the signal levels detected by said plurality of level detector circuits, taking advantage of idle mode duration; and

an interference attenuation retaining circuit which retains a value of attenuation evaluated by said interference attenuation evaluating circuit during a receiving mode,

wherein each of said gain control circuits controls the gain of one which is connected thereto of said variable gain amplifiers, based on information of the value of attenuation of interference signals retained during said receiving mode and the signal level detected and output by one which is connected thereto of said plurality of level detector circuits.

5. A receiver circuit comprising:

a variable gain low-noise amplifier which amplifies received high frequency signals;

a mixer which converts a signal output from said variable gain low-noise amplifier into an intermediate frequency signal;

a variable gain circuit which amplifies a signal output from the mixer;

a first level detector circuit which detects the signal level of said variable gain low-noise amplifier;

a first gain control circuit which controls the gain of said variable gain low-noise amplifier;

a second level detector circuit which detects the signal level of said variable gain circuit; and

a second gain control circuit which controls the gain of said variable gain circuit,

wherein said first gain control circuit controls the gain of said variable gain low-noise amplifier, based on the signal level detected by said first level detector circuit, and supplies information about the gain control to said second gain control circuit, and

wherein said second gain control circuit controls the gain of said variable gain circuit, based on the signal level detected by said second level detector circuit and said information about the gain control.

6. The receiver circuit according to claim 5,

wherein said variable gain circuit comprises one or a plurality of variable gain amplifiers and one or a plurality of filters,

wherein said second level detector circuit detects signal levels at respective inputs of said variable gain amplifiers, and

wherein said second gain control circuit controls the gain or gains of said one or plurality of variable gain amplifiers.

7. The receiver circuit according to claim 6,

wherein said first level detector circuit is connected to the inputs of said variable gain amplifiers.

8. The receiver circuit according to claim 5,

wherein said variable gain circuit comprises one or a plurality of variable gain amplifiers and one or a plurality of filters,

wherein said second level detector circuit detects signal levels at respective outputs of said variable gain amplifiers, and

wherein said second gain control circuit controls respective gains of said variable gain amplifiers.

9. The receiver circuit according to claim 5, further comprising:

a plurality of filters separately connected to respective outputs of said plurality of variable gain amplifiers; and

a filtered attenuation evaluating circuit which evaluates the quantity of signal attenuation by said plurality of filters, based on the signal levels detected by said plurality of level detector circuits,

wherein said gain control circuit controls the respective gains of said variable gain amplifiers, based on signal attenuation evaluated by said filtered attenuation evaluating circuit and the signal levels detected and output by said plurality of level detector circuits.

10. The receiver circuit according to claim 5, further comprising:

a plurality of filters separately connected to respective outputs of said plurality of variable gain amplifiers;

an interference attenuation evaluating circuit which evaluates the quantity of attenuation of interference signals, based on the signal levels detected by said plurality of level detector circuits, taking advantage of idle mode duration; and

an interference attenuation retaining circuit which retains a value of attenuation evaluated by said interference attenuation evaluating circuit during a receiving mode,

wherein said gain control circuit controls the respective gains of said variable gain amplifiers, based on information of the value of attenuation of interference signals retained during said receiving mode and the signal levels detected and output by said plurality of level detector circuits.

11. and 12. (Cancel)