Memory controller with power management logic

• US 20040230739A1
• Filed: 06/21/2004
• Published: 11/18/2004
• Est. Priority Date: 07/19/2000
• Status: Active Grant

• Current Assignee: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
• Original Assignee: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
• Inventors: Barth, Richard M., Tsern, Ely K., Woo, Steven C., Satagopan, Ramprasad
• Granted Patent: US 7,003,639 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

Claims

1. A memory controller for controlling a plurality of dynamic memory devices, comprising:

device state logic for determining a power state for each memory device of the plurality of dynamic memory devices, including logic for setting the determined power state of at least one respective memory device to a predefined active power state, for setting the determined power state of a second respective memory device to a predefined low-power state, and for setting the determined power state of a third respective memory device to a predefined mid-power state; and

command issue circuitry configured to issue power state commands to the dynamic memory devices in accordance with the power state determined by the device state logic, wherein the command issue circuitry is configured to issue a mid-power state command to the third respective memory device.

2. The memory controller of claim 1, wherein the device state logic is configured to set the determined power state of a respective memory device to the predefined active power state if a first operating condition is satisfied, to the predefined low-power state if a second operating condition is satisfied, and to the predefined mid-power state if a third operating condition is satisfied.

3. The memory controller of claim 1, wherein the mid-power state uses less power than the active power state, and the low power state uses less power than the mid-power state.

4. The memory controller of claim 1, wherein the memory controller implements a predefined open page policy wherein any page in any of the memory devices that is opened in response to a first memory access request is kept open for possible access by a subsequent memory access request until a predefined page close condition requires the page to be closed.

5. The memory controller of claim 4, including a cache configured to store open page status information identifying each open page of the plurality of dynamic memory devices in the predefined active state, wherein the command issue circuitry includes additional logic that utilizes the open page status information stored in the cache to generate a command selection signal when an address in a memory access request corresponds to a memory device for which open page status information is stored in the cache.

6. The memory controller of claim 5, wherein the command issue circuitry utilizes the open page status information stored in the cache to generate the access commands to the dynamic memory devices, so as to access memory locations in an open page without performing a precharge operation if the memory access request corresponds to memory locations in an open page.

7. A memory controller, comprising:

memory configured to store a power state for at least one memory device in a memory system, wherein the power state is from a set of power states including a first power state, a second power state and a third power state, wherein the power states are associated with different levels of power supplied to the memory device; and

a command issue circuit coupled to the memory and the memory device, the command issue circuit configured to transition the memory device between power states based at least in part on a memory access request associated with the memory device.

8. The memory controller of claim 7, wherein the first power state is an active power state, the second power state is a mid-power state and the third power state is a low power state.

9. The memory controller of claim 7, wherein the command issue circuit is configured to transition the memory device between power states based at least in part on a power management policy.

10. The memory controller of claim 9, wherein the power management policy is an open-page policy.

11. The memory controller of claim 9, wherein the power management policy is a closed-page policy.

12. The memory controller of claim 7, wherein the memory device is assigned to a subset of memory devices in the memory system that are associated with a power state.

13. The memory controller of claim 7, wherein the memory is configured for storing entries that indicate a current power state for memory devices, wherein some of the entries include a maximum number of entries specifying memory devices in a second power state.

14. The memory controller of claim 13, wherein the command issue circuit issues power state commands and access commands to the memory device in accordance with at least one command selection signal and an address in a memory access request associated with the memory device.

15. A method of controlling the power states of memory devices in a memory system using a memory controller, comprising:

at the memory controller;

receiving a memory access request;

determining a current power state of at least one memory device, wherein the current power state is determined from a set of power states including a low power state, a mid-power state and an active state; and

issuing a power state command to the memory device, wherein the power state command causes the memory device to transition to a new power state different from the current power state.

16. The method of claim 15, wherein the new power state is determined at least in part by a power management policy.

17. The method of claim 16, wherein the power management policy is an open-page policy.

18. The method of claim 16, wherein the power management policy is a closed-page policy.

19. The method of claim 15, wherein determining the memory device'"'"'s current power state includes retrieving current power state information and fullness information from a cache, wherein the fullness information indicates whether the current power state information indicates a maximum number of memory devices that are in a mid-power state.

20. A memory control system for controlling the power states of memory devices in a memory system, the memory control system comprising:

means for receiving a memory access request;

means for determining a current power state for at least one memory device, wherein the current power state is determined from a set of power states including a low power state, a mid-power state and an active state; and

means for issuing a power state command to the memory device, wherein the power state command causes the memory device to transition to a new power state different from the current power state.