Concurrent program loading and execution

• US 20040230784A1
• Filed: 05/12/2003
• Published: 11/18/2004
• Est. Priority Date: 05/12/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Cohen, Eugene M.
• Application Number:
  US10/436,727
• Publication Number:
  US 20040230784A1
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading

Abstract

Systems and methods for concurrently loading and executing a computer program allow for beginning execution of a computer program while the computer program is being loaded into a primary memory for access by a processor.

Claims

1. A method comprising:

initiating copying of a portion of a computer program to a specified set of addresses in a memory; and

before the portion has been entirely copied to the specified set of addresses,

executing an invalid instruction handling routine in response to detection of an invalid instruction at a given address in the specified set of addresses; and

loading a valid instruction at the given address after detection of the invalid instruction.

2. A method as defined in claim 1, further comprising executing the valid instruction at the given address after execution of the invalid instruction handling routine has completed.

3. A method as defined in claim 2, wherein copying the portion of the computer program to the specified set of addresses in the memory is carried out by a first processor.

4. A method as defined in claim 3, wherein executing the valid instruction at the given address is carried out by a second processor.

5. A method as defined in claim 4, wherein loading the valid instruction at the given address is carried out by the first processor.

6. A method as defined in claim 4, wherein loading the valid instruction at the given address is carried out by the second processor.

7. A method as defined in claim 4, wherein the first processor comprises a Direct Memory Access (DMA) controller.

8. A method as defined in claim 4, wherein prior to initiating copying of the portion of the computer program to the specified set of addresses in the memory invalid instructions are written to each of the addresses in the specified set of addresses.

9. A method as defined in claim 8, wherein the invalid instruction handling routine controls the loading of the valid instruction at the given address.

10. A method as defined in claim 9, wherein the invalid instruction handling routine is carried out by the second processor.

11. A method as defined in claim 4, wherein the invalid instruction handling routine instructs the second processor to perform the following operations:

saving context of the second processor; and

restoring context of the second processor in response to the loading of the valid instruction at the given address.

12. A method as defined in claim 11, wherein the loading of the valid instruction at the given address is performed by the first processor.

13. A method as defined in claim 11, wherein the loading of the valid instruction at the given address is performed by the second processor.

14. A method as defined in claim 4, wherein the invalid instruction handling routine instructs the second processor to perform the following operations:

saving context of the second processor;

signaling the first processor to suspend copying the portion of the computer program to the specified set of addresses in the memory;

loading of the valid instruction at the given address;

signaling the first processor to resume copying the portion of the computer program to the specified set of addresses in the memory; and

restoring context of the second processor.

15. A method as defined in claim 1, wherein initiating copying of the portion of the computer program to the specified set of addresses in the memory comprises:

sending an instruction to a Direct Memory Access (DMA) controller to copy the portion of the computer program from a non-volatile memory to the specified set of addresses in the memory.

16. A method as defined in claim 15, wherein the memory comprises Random Access Memory (RAM).

17. A method as defined in claim 16, wherein prior to initiating copying invalid instructions are copied to each of the specified set of addresses in the memory.

18. A method as defined in claim 16, wherein the invalid instruction handling routine is executed by a microprocessor and wherein the microprocessor sends the instruction to the DMA controller to copy the portion of the computer program from the non-volatile memory to the specified set of addresses in the memory.

19. A system comprising:

a first processor configured to perform a write operation comprising writing a specified portion of a computer program including instructions into designated addresses of a memory; and

a second processor configured to access and execute the program instructions from the designated addresses of the memory concurrently with a performance of the write operation by the first processor.

20. A system as defined in claim 19, wherein the first processor comprises a Direct Memory Access (DMA) controller.

21. A system as defined in claim 19, wherein the second processor is further configured to suspend execution of the program instructions in response to a detection of an invalid instruction at a particular address in the designated addresses of the memory.

22. A system as defined in claim 21, wherein the second processor is further configured resume execution of the program instructions following the suspension of the execution of the program instructions in response to a detection of a valid instruction at the particular address in the designated address of the memory.

23. A system as defined in claim 22, wherein the second processor is further configured to write a valid instruction at the particular address in response to the detection of the invalid instruction at the particular address.

24. A system as defined in claim 22, wherein the second processor is further configured to instruct the first processor to write a valid instruction at the particular address in response to the detection of the invalid instruction at the particular address.

25. A system as defined in claim 21, wherein the second processor is further configured to perform a context save operation in response to the detection of the invalid instruction at the particular address and prior to suspending execution of the program instructions.

26. A system as defined in claim 19 wherein the first processor is further configured to perform the following operations in response to the detection of the invalid instruction:

performing a context save operation;

suspending execution of the program instructions;

writing a valid instruction at the particular address;

performing a context restore operation; and

continuing execution of the program instructions.

27. A system as defined in claim 19 wherein the first processor is further configured to perform the following operations in response to the detection of the invalid instruction:

performing a context save operation;

suspending execution of the program instructions;

detecting a valid instruction at the particular address;

performing a context restore operation; and

continuing execution of the program instructions.

28. A system comprising:

a primary memory;

a Direct Memory Access (DMA) controller operably connected to the primary memory; and

a microprocessor operably connected to the primary memory and the DMA controller, wherein the microprocessor is configured to,

cause the DMA controller to load a specified portion of a computer program including program instructions into designated addresses of the primary memory; and

execute the program instructions from the designated addresses of the memory concurrently with the loading by the DMA controller of the specified portion of the computer program into the designated addresses of the primary memory.

29. A system as defined in claim 28, wherein the microprocessor is further configured to execute an invalid instruction handling routine in response to detection of an invalid instruction at one of the designated addresses.

30. A system as defined in claim 29, wherein execution of the invalid instruction handling routine causes the DMA controller to suspend loading of the specified portion of the computer program into the designated addresses of the primary memory until a valid instruction is loaded into the one of the designated addresses.

31. A system as defined in claim 30, wherein execution of the invalid instruction handling routine further causes the microprocessor to load a valid instruction into the one of the designated addresses.

32. A system as defined in claim 28, wherein the microprocessor is further configured to load an initial portion of the computer program into the primary memory prior to causing the DMA controller to load the specified portion of the computer program into the designated addresses of the primary memory.

33. A system as defined in claim 32, wherein the initial portion of the computer program includes a program entry point.

34. A computer-readable medium having computer-executable instructions for performing acts comprising:

loading a computer program into a memory; and

executing instructions of the computer program concurrently with the loading of the computer program into the memory.

35. A computer-readable medium as defined in claim 34, wherein the act of loading the computer program comprises:

instructing a first processor to load a first portion of the computer program; and

instructing a second processor to load a second portion of the computer program.

36. A computer-readable medium as defined in claim 34, wherein the computer program consists of a first portion and a second portion and wherein the act of loading the computer program comprises:

instructing a first processor to load the first portion of the computer program; and

instructing a second processor to load the second portion of the computer program.

37. A computer-readable medium as defined in claim 34, further having computer-executable instructions for performing acts comprising:

executing an invalid instruction handling routine in response to the detection of an invalid instruction at a particular address in the memory.

38. A computer-readable medium as defined in claim 37, wherein the instruction handling routine comprises computer-executable instructions for performing acts comprising:

performing a context save operation;

suspending execution of the computer program;

detecting a valid instruction at the particular address in the memory;

performing a context restore operation; and

terminating the suspension of the execution of the computer program.

39. A computer-readable medium as defined in claim 37, wherein the instruction handling routine comprises computer-executable instructions for performing acts comprising:

performing a context save operation;

suspending execution of the computer program;

writing a valid instruction at the particular address;

performing a context restore operation; and

terminating the suspension of the execution of the computer program.