Power saving in FPU with gated power based on opcodes and data

• US 20040230849A1
• Filed: 05/15/2003
• Published: 11/18/2004
• Est. Priority Date: 05/15/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, Sang Hoo, Mueller, Silvia Melitta, Oh, Hwa-Joon
• Granted Patent: US 7,137,021 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and an apparatus are provided for saving power in a microprocessor. The microprocessor has at least one functional unit, which has a plurality of blocks. The blocks each include a plurality of sub-blocks. It is determined whether there is any instruction for the functional unit. Upon a determination that there is no instruction for the functional unit, the functional unit is shut down. Upon a determination that there is at least one instruction for the functional unit, at least one inactive block of the functional unit is shut down based on the instruction.

Claims

1. A method for saving power in a microprocessor having at least one functional unit having a plurality of blocks each including a plurality of sub-blocks, the method comprising the steps of:

determining whether there is any instruction for the at least one functional unit;

upon a determination that there is no instruction for the at least one functional unit, shutting down the at least one functional unit; and

upon a determination that there is at least one instruction for the at least one functional unit, wherein the at least one functional unit has at least one inactive block and at least one active block, shutting down the at least one inactive block based on the at least one instruction.

2. The method of claim 1, further comprising the step of, for the at least one active block, wherein the at least one active block has at least one inactive sub-block, shutting down the at least one inactive sub-block based on the at least one instruction.

3. The method of claim 1, wherein the at least one inactive block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

4. The method of claim 2, wherein the at least one inactive sub-block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

5. The method of claim 1, wherein the functional unit is a floating-point unit (FPU).

6. The method of claim 5, wherein the at least one active block is an adder block.

7. An apparatus for saving power in a microprocessor having at least one functional unit having a plurality of blocks each including a plurality of sub-blocks, the apparatus comprising:

means for determining whether there is any instruction for the at least one functional unit;

means for, upon a determination that there is no instruction for the at least one functional unit, shutting down the at least one functional unit; and

means for, upon a determination that there is at least one instruction for the at least one functional unit, wherein the at least one functional unit has at least one inactive block and at least one active block, shutting down the at least one inactive block based on the at least one instruction.

8. The apparatus of claim 7, further comprising means for, for the at least one active block, wherein the at least one active block has at least one inactive sub-block, shutting down the at least one inactive sub-block based on the at least one instruction.

9. The apparatus of claim 7, wherein the at least one inactive block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

10. The apparatus of claim 8, wherein the at least one inactive sub-block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

11. The apparatus of claim 7, wherein the functional unit is a floating-point unit (FPU).

12. The apparatus of claim 11, wherein the at least one active block is an adder block.

13. A computer program product for saving power in a microprocessor having at least one functional unit having a plurality of blocks each including a plurality of sub-blocks, the computer program product having a medium with a computer program embodied thereon, the computer program comprising:

computer program code for determining whether there is any instruction for the at least one functional unit;

computer program code for, upon a determination that there is no instruction for the at least one functional unit, shutting down the at least one functional unit; and

computer program code for, upon a determination that there is at least one instruction for the at least one functional unit, wherein the at least one functional unit has at least one inactive block and at least one active block, shutting down the at least one inactive block based on the at least one instruction.

14. The computer program product of claim 13, the computer program further comprising computer program code for, for the at least one active block, wherein the at least one active block has at least one inactive sub-block, shutting down the at least one inactive sub-block based on the at least one instruction.

15. The computer program product of claim 13, wherein the at least one inactive block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

16. The computer program product of claim 14, wherein the at least one inactive sub-block is shut down based on both the at least one instruction and one or more operands used to execute the at least one instruction.

17. The computer program product of claim 13, wherein the functional unit is a floating-point unit (FPU).

18. The computer program product of claim 17, wherein the at least one active block is an adder block.

19. In a microprocessor, an apparatus for saving power consumed in a functional unit of the microprocessor, the functional unit having a plurality of cycles, the apparatus comprising:

a control logic circuit coupled to the functional unit, the control logic being configured for receiving one or more instructions and operands to be executed in the functional unit and for shutting down one or more inactive portions of the functional unit, the one or more inactive portions being determined based on the one or more instructions and the associated operands; and

a sequencer circuit coupled to the control logic and to the functional unit, the sequencer circuit being configured for detecting which cycle in an active portion of the functional unit the operands are currently in and for shutting down any inactive cycles in the active portions of the functional unit.

20. The apparatus of claim 19, wherein the functional unit is a floating-point unit (FPU).

21. The apparatus of claim 19, wherein each of the plurality of cycles is gated by one of a plurality of latches, and wherein the sequencer circuit is coupled to the plurality of latches for controlling the latches.

22. The apparatus of claim 19, further comprising a lookup table coupled to the control logic circuit, wherein the lookup table contains information on signals that control clock gating of the functional unit based on the instructions and the operands.