Compressing test responses using a compactor

• US 20040230884A1
• Filed: 02/13/2004
• Published: 11/18/2004
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Granted Patent: US 7,370,254 B2
• Time in Patent Office: Days
• US Class Current: 714/742
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

Claims

1. A method for testing a circuit-under-test, comprising:

providing a set of test-response values from the circuit-under-test, the set of test-response values comprising a plurality of S test-response values;

expanding the S test-response values into a plurality of V expanded test values, wherein V is greater than S;

producing T primary intermediate values from at least some of the V expanded values;

producing U secondary intermediate values by combining at least a portion of the T primary intermediate values with previously stored intermediate values;

storing at least one of the U secondary intermediate values for one or more clock cycles; and

outputting B output values at least partially determined by the U secondary intermediate values during an observation period of two or more clock cycles, wherein the B output values in the observation period are indicative of one, two, and odd-numbered errors present in the set of test-response values.

2. The method according to claim 1, wherein the act of expanding the S test-response values comprises fanning out the S test-response values through polynomial combinations of gates, the polynomial combinations of gates being selected to provide nonmasking patterns for producing the T primary intermediate values from the S test-response values.

3. The method of claim 1, comprising means for diagnosing faults in the circuit-under-test from the B output values.

4. The method according to claim 1, wherein B is less than S.

5. The method according to claim 4, wherein B is one hundred times less than S.

6. The method according to claim 1, wherein the acts of expanding the S test-response values, producing the T primary intermediate values, producing the U secondary intermediate values, and outputting the B output values during the observation period are performed with feedback-free logic.

7. The method of claim 1, wherein the set of test-response values corresponds to test-response values clocked out of scan chains in the digital circuit-under-test during a single clock cycle.

8. An integrated circuit comprising a compactor configured to perform the method of claim 1.

9. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform the method of claim 1.

10. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 1.

11. A method for compressing a test response in an integrated circuit, comprising:

inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

producing at least two intermediate values at least partially determined by the test value via logic;

loading at least a portion of the intermediate values into plural memory elements;

producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

outputting the set of at least two output values over an observation period, the observation period comprising at least two clock cycles and ending before the unloading period ends.

12. The method of claim 11, further comprising determining whether the test value is an expected test value by analyzing the set of output values.

13. The method of claim 11, further comprising locating a source of an error in the integrated circuit based on the set of output values.

14. The method of claim 11, wherein an unknown test value is input into the logic during a time associated with the observation period, and wherein the set of output values is at least partially unaffected by the unknown test value.

15. The method of claim 11, wherein the set of at least two output values comprises at least two output values that are output simultaneously from different respective memory elements.

16. The method of claim 11, wherein at least two of the memory elements are connected via feedback-free logic.

17. The method of claim 11, wherein the plural memory elements at least partially comprise one or more registers.

18. The method of claim 11, in which the act of producing the at least two output values comprises the act of serially shifting at least some of the intermediate values through the memory elements.

19. The method of claim 11, wherein the observation period is less than one half of the unloading period.

20. The method of claim 11, wherein the observation period is less then one hundredth of the unloading period.

21. A method for testing an integrated circuit, comprising repeating the acts of claim 11 for a plurality of the test values.

22. A method for testing an integrated circuit, wherein the acts of claim 11 are performed simultaneously for multiple different test values, and wherein the logic is configured to eliminate one, two, or odd-numbered error masking.

23. An integrated circuit comprising a compactor configured to perform the method of claim 11.

24. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform the method of claim 11.

25. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 11.

26. A method for compressing a test response in an integrated circuit, comprising:

inputting a test value into a network comprising combinational logic, the test value being input from one of multiple scan cells in a scan chain during an unloading period;

expanding the test value through at least two fan-outs in the network;

producing two or more intermediate values from the expanded test values;

loading the intermediate values into plural memory elements; and

outputting two or more output values from the plural memory elements over an observation period of at least two clock cycles,

wherein the output values are at least partially determined by the intermediate values and the test value, and wherein the number of output values equals the number of the fan-outs.

27. The method of claim 26, wherein the fan-outs are effective fan-outs.

28. The method of claim 26, wherein the number of the fan-outs is odd-numbered.

29. The method of claim 28, wherein the number of the fan-outs is three, five, or seven.

30. The method of claim 26, wherein the observation period ends before the unloading period ends.

31. An integrated circuit comprising a compactor configured to perform the method of claim 26.

32. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform the method of claim 26.

33. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 26.

34. A method for testing an integrated circuit, comprising:

capturing multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;

clocking the test values out of the scan chain and into a compactor;

producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value; and

outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.

35. The method of claim 34, wherein the act of producing the sets of two or more output values comprises:

producing intermediate values via logic; and

loading the intermediate values into a plurality of memory elements.

36. The method of claim 35, wherein the plurality of memory elements are at least partially coupled by feedback-free logic.

37. The method of claim 34, further comprising locating a source of an error in the scan chain based on the output values.

38. The method of claim 34, further comprising means for diagnosing faults in the test value using the sets of two or more output values.

39. An integrated circuit comprising a compactor configured to perform the method of claim 34.

40. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform the method of claim 34.

41. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 34.

42. A method for compressing test responses of a circuit-under-test, comprising:

injecting a first portion of a test response and a second portion of the test response into a network comprising combinational logic;

logically producing in the network a first set of two or more primary intermediate values at a first set of network outputs, the first set of primary intermediate values being at least partially determined by the first portion of the test response;

logically producing in the network a second set of two or more primary intermediate values at a second set of network outputs, the second set of primary intermediate values being at least partially determined by the second portion of the test response, the second set of network outputs having at least one network output that is mutually exclusive of the first set of network outputs;

at least partially combining the first set of primary intermediate values with a first set of previously stored values to produce a first set of secondary intermediate values;

at least partially combining the second set of primary intermediate values with a second set of previously stored values to produce a second set of secondary intermediate values;

loading the first set of secondary intermediate values into a first set of memory elements coupled to the first set of network outputs; and

loading the second set of secondary intermediate values into a second set of memory elements coupled to the second set of network outputs, the second set of memory elements comprising a nonshifted set of memory elements relative to the first set of memory elements.

43. The method of claim 42, wherein the first portion of the test response is a first test value and the second portion of the test response is a second test value, the method further comprising clocking the memory elements to produce a first set of output values associated with the first test value and a second set of output values associated with the second test value, the second set of output values always being distinguishable from the first set of output values.

44. The method of claim 43, wherein the first set of output values is clocked out of the memory elements during a first observation period, and the second set of output values is clocked out of the memory elements during a second observation period, the first observation period ending at a different time than the second observation period.

45. The method of claim 43, wherein the first set of output values is clocked out of the memory elements during a first observation period, and the second set of output values is clocked out of the memory elements during a second observation period, the first observation period beginning before the second observation period and ending after the second observation period.

46. The method of claim 43, wherein the first and second test values are error values.

47. The method of claim 43, wherein one of the first and second test values is an unknown value.

48. The method of claim 42, wherein at least some of the memory elements are serially connected via feedback-free logic.

49. An integrated circuit comprising a compactor configured to perform the method of claim 42.

50. A computer-readable medium storing computer-executable instructions for causing a computer system to design a compactor configured to perform the method of claim 42.

51. A computer-readable medium storing a design database that includes design information for a compactor configured to perform the method of claim 42.

52. An apparatus for compressing test responses in an integrated circuit, comprising:

a plurality of memory elements; and

an injector network comprising combinational logic, the injector network having injector-network outputs and injector-network inputs,

each injector-network output being coupled to a respective one of the memory elements,

each injector-network input being logically coupled to two or more injector-network outputs according to a respective injector polynomial, the respective injector polynomial being selected to prevent one, two, and odd-numbered error masking in the memory elements.

53. The apparatus of claim 52, wherein two or more of the memory elements are further coupled in series via feedback-free logic.

54. The apparatus of claim 53, wherein the feedback-free logic combines serially shifted values from the two or more memory elements with respective values from the injector-network outputs.

55. The apparatus of claim 52, wherein the two or more memory elements output a series of output values associated with a test value injected in a single clock cycle, the series of output values being output over a fixed period of clock cycles.

56. The apparatus of claim 52, wherein the plurality of memory elements are serially connected to one another via logic that includes at least one feedback loop.

57. The apparatus of claim 52, wherein the plurality of memory elements form a multiple input signature register (MISR).

58. The apparatus of claim 57, wherein the injector network prevents MISR cancellation in the MISR.

59. The apparatus of claim 52, further comprising a bypass network coupled between the injector-network inputs and scan-chain outputs.

60. The apparatus of claim 52, further comprising a selector circuit coupled between the injector-network inputs and scan-chain outputs, the selector circuit being operable to mask one or more of the scan-chain outputs.

61. The apparatus of claim 52, further comprising at least one serial-input-parallel-output register coupled between at least one scan-chain and two or more of the injector-network inputs.

62. The apparatus of claim 52, further comprising at least one scan chain having multiple outputs coupled to one or more of the injector-network inputs.

63. The apparatus of claim 52, further comprising means for diagnosing output values output from the plurality of memory elements.

64. A computer-readable medium storing computer-executable instructions for causing a computer system to design the apparatus of claim 52.

65. A computer-readable medium storing a design database that includes design information for the apparatus of claim 52.

66. An apparatus for compressing test responses in a digital circuit, comprising:

a plurality of memory elements; and

an injector network comprising combinational logic, the injector network having injector-network outputs and injector-network inputs,

each injector-network output being coupled to a respective one of the memory elements,

each injector-network input being logically coupled to two or more injector-network outputs according to a respective injector polynomial, the respective injector polynomial being selected to prevent masking of an unknown value in the memory elements.

67. The apparatus of claim 66, wherein the respective injector polynomial is further configured to prevent one, two, and odd-numbered error masking in the memory elements.

68. The apparatus of claim 66, further comprising means for diagnosing output values that are output from the plurality of memory elements.

69. A method for compressing a test response in an integrated circuit, comprising:

means for inputting a test value from one of multiple scan cells in a scan chain during an unloading period of the scan chain;

means for producing at least two intermediate values at least partially determined by the test value in a network comprising combinational logic;

means for loading at least a portion of the intermediate values into plural memory elements;

means for producing a set of at least two output values at least partially determined by the intermediate values, the set of at least two output values comprising all output values at least partially determined by the intermediate values; and

means for outputting the set of at least two output values over an observation period, the observation period comprising at least two clock cycles and ending before the unloading period ends.

70. A method for designing a compactor to compress test responses captured by scan chains in a circuit-under-test, comprising:

inputting design data concerning the circuit-under-test, the design data comprising the number of scan-chain outputs in the circuit-under-test;

generating at least two injector polynomials for connecting the scan-chain outputs of the circuit-under-test to plural memory elements of the compactor, the at least two injector polynomials being configured to prevent one, two, and odd-numbered error masking in the plural memory elements, the plural memory elements being coupled together by a feedback-free network; and

selecting at least one of the polynomials.

71. The method of claim 70, wherein the at least two injector polynomials are further configured to prevent masking of an unknown test value in the plural memory elements.

72. The method of claim 70, wherein the selecting is performed randomly.

73. The method of claim 70, further comprising producing an injector network that couples each scan-chain output to at least two of the plural memory elements of the compactor according to a respective one of the injector polynomials selected.

74. A computer-readable medium storing computer-executable instructions for causing a computer system to perform the method of claim 70.

75. A method for designing a compactor to compress test responses provided by scan chains of a circuit-under-test, comprising:

generating a list of valid polynomials that represent non-masking patterns for coupling outputs of the scan chains to combinations of plural memory elements in the compactor;

selecting one of the polynomials from the list of valid polynomials;

logically combining the selected polynomial with two or more previously selected polynomials using an XOR or XNOR operation, thereby determining a forbidden polynomial that masks the selected polynomial; and

removing the forbidden polynomial from the list of valid polynomials.

76. The method of claim 75, wherein the valid polynomials prevent one, two, and odd-numbered error masking in the compactor.

77. The method according to claim 75, wherein the act of selecting one of the polynomials comprises randomly selecting said one of the polynomials.

78. The method of claim 75, wherein the two or more previously selected polynomials are a pair of previously selected polynomials, and the logically combining act is repeated for each selected polynomial and each pair of previously selected polynomials.

79. A computer-readable medium storing computer-executable instructions for causing a computer system to perform the method of claim 75.