Power MOS device with improved gate charge performance

• US 20040232407A1
• Filed: 03/17/2003
• Published: 11/25/2004
• Est. Priority Date: 12/20/1999
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Calafut, Daniel S.
• Application Number:
  US10/391,126
• Publication Number:
  US 20040232407A1
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Claims

1. A method of fabricating a gate structure of a DMOS device, comprising the steps of:

forming a polysilicon gate on a portion of a semiconductor substrate;

implanting a dopant of a first conductivity type into the polysilicon gate;

masking the polysilicon gate to define an alternation region within the gate; and

implanting a dopant of a second conductivity type into the alternation region, where the second conductivity type has an electrical polarity opposite a polarity of the first conductivity type.

2. The method of claim 1, wherein the step of forming a polysilicon gate further comprises the steps of:

growing a dielectric layer on the semiconductor substrate;

depositing a polysilicon layer on the dielectric layer; and

masking the polysilicon layer to define a polysilicon gate.

3. The method of claim 1, wherein the step of implanting a dopant of a second conductivity type further comprises diffusing the dopant of the second conductivity type to drive the dopant to an outer boundary of the alternation region.

4. The method of claim 1, wherein the polarity of the first conductivity type is n-type and the polarity of the second conductivity type is p-type.

5. The method of claim 1, wherein the polysilicon gate overlies a channel region in the semiconductor substrate and extends at least partially over a source formed in the substrate, and wherein an extent of the alternation region corresponds to a boundary between the channel region and an accumulation area.

6. A gate of a semiconductor device, comprising:

a polysilicon gate structure overlying a channel region in a semiconductor substrate and extending at least partially over a source formed in the substrate adjacent the channel region, the polysilicon gate structure having a first portion being of a first conductivity type and a second portion being of a second conductivity type defining an alternation region.

7. The device as in claim 6, wherein an extent of the alternation region substantially corresponds to a boundary between the channel region and an accumulation area in the semiconductor substrate.

8. The device as in claim 6, wherein an electrical polarity of the first conductivity type is opposite an electrical polarity of the second conductivity type.

9. The device as in claim 8, wherein the first portion of the polysilicon gate is doped with n-type impurities.

10. The device as in claim 9, wherein the second portion of the polysilicon gate is doped with p-type impurities.

11. The device as in claim 10, wherein the p-type impurities are boron ions, and wherein the n-type impurities are ions selected from the group comprised of arsenic and phosphorous.

12. The device as in claim 6, further comprising a polycide layer disposed over the polysilicon gate structure.

13. A method of fabricating a gate structure of a DMOS device, comprising the steps of:

forming a trench in a semiconductor substrate;

lining the trench with a dielectric layer;

forming a first polysilicon gate portion to an intermediate depth of the trench;

implanting a dopant of a first conductivity type into the first gate portion;

forming a second polysilicon gate portion in the trench over the first gate structure to a level substantially equal to a top surface of the silicon substrate; and

implanting a dopant of a second conductivity type into the second gate portion.

14. The method of claim 13, further comprising the steps of:

etching away an intermediate portion of the second polysilicon gate portion down to the first polysilicon gate portion; and

forming a polycide strap layer over the first polysilicon gate layer in the intermediate portion and on opposite side walls of the second polysilicon gate portion.

15. The method of claim 14, further comprising the step of depositing a conductive material in the intermediate portion to the level substantially equal to the top surface of the silicon substrate.

16. A composite gate structure in a trench transistor, comprising:

a trench extending a selected depth from a top surface of a semiconductor substrate;

a conformal dielectric layer lining the trench;

a first gate portion disposed over the dielectric layer and extending from the bottom to an intermediate depth of the trench, the first gate portion having a first conductivity type; and

a second gate portion disposed over the first gate portion and the dielectric layer, and extending from the intermediate depth to the top surface, the second gate portion having a second conductivity type that is of an opposite polarity from the first conductivity type.

17. The gate structure of claim 16, further comprising a polycide layer disposed on two side portions of the second gate portion, and over a mid-portion of the first gate portion.

18. The gate structure of claim 16, wherein the first conductivity type is p-type and the second conductivity type is n-type.

19. The gate structure of claim 16, wherein the first gate portion is formed by implanting a dopant of the first conductivity type into polysilicon comprising the first gate portion.

20. The gate structure of claim 16, wherein the second gate portion is formed by implanting a dopant of the second conductivity type into polysilicon comprising the second gate portion.

21. The gate structure of claim 17, wherein the two side portions of the second gate portion are formed by etching away a mid-portion of the second gate portion.

22. The gate structure of claim 16, wherein the intermediate depth substantially corresponds to a boundary between a source region and an epitaxial layer in the substrate.

23. A semiconductor device, comprising:

a channel region of a first conductivity type formed by diffusing a dopant of the first conductivity type into a substrate having a second conductivity type;

a gate dielectric disposed on the substrate; and

an implant region of a second conductivity type formed by diffusing a dopant of the first conductivity type under the gate dielectric, the second conductivity type having a polarity opposite a polarity of the first conductivity type.

24. The semiconductor device of claim 23, wherein the gate dielectric conforms to a trench in the substrate.