Interconnect routing over semiconductor for editing through the back side of an integrated circuit

• US 20040232414A1
• Filed: 05/19/2003
• Published: 11/25/2004
• Est. Priority Date: 05/19/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Suthar, Sailesh C., Sarwar, Syed N., Hack, Paul J.
• Granted Patent: US 7,199,039 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

Circuit edits may be performed through the back side of an integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. An insulating layer is not deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, a conductor is deposited over the circuit edit connection targets from the back side of the integrated circuit to couple together the circuit edit connection targets.

Claims

1. A method comprising:

exposing, from a back side of the integrated circuit die, edit connection targets through a semiconductor substrate of the integrated circuit die; and

depositing a conductor directly on the substrate from the first to the second circuit edit connection targets.

2. The method of claim 1 including thinning the semiconductor substrate of the integrated circuit die from the back side of the integrated circuit die.

3. The method of claim 1 including depositing the conductor using a focused ion beam metal deposition.

4. The method of claim 1 including depositing the conductor using a laser induced metal deposition.

5. The method of claim 1 including depositing said conductor in one step.

6. The method of claim 1 including forming said conductor with vertical and horizontal portions and forming said portions in one step.

7. The method of claim 1 including forming contact vias to said targets and making contact to said targets, filing said vias, and connecting said vias in one step.

8-15. -15. (Canceled).

16. A method comprising:

exposing from a back side of an integrated circuit die, first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die; and

depositing in one step a conductor over the substrate between the first and second circuit edit connection targets to couple together the first and second circuit edit connection targets.

17. The method of claim 16 including depositing said conductor directly on the substrate.

18. The method of claim 16 including forming the conductor using focused ion beam metal deposition.

19. The method of claim 16 including forming said conductor using laser induced metal deposition.

20. The method of claim 16 including forming vertically extending and horizontally extending portions of said conductor in one step.

21. The method of claim 16 including contacting said conductor to said targets and connecting said targets in one step.