Methods of forming vertical power devices having trench-based source electrodes with sidewall source contacts

• US 20040232479A1
• Filed: 06/21/2004
• Published: 11/25/2004
• Est. Priority Date: 04/11/2001
• Status: Abandoned Application

• Current Assignee: Bantval Jayant Baliga
• Original Assignee: Bantval Jayant Baliga
• Inventors: Baliga, Bantval Jayant
• Application Number:
  US10/873,102
• Publication Number:
  US 20040232479A1
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode

Abstract

Methods of forming vertical power devices include the steps of forming a lateral-channel MOSFET having a base region of second conductivity type within the semiconductor substrate and a source region of first conductivity type within the base region. A trench is also formed in the semiconductor substrate. The trench has sidewalls that define an interface with the source and base regions. The sidewalls of the trench are lined with a trench insulating layer and an electrically conductive region is formed on the trench insulating layer. An upper portion of the trench insulating layer is removed to expose a portion of the base region extending along the interface. A source electrode is then formed that ohmically contacts the source region, the exposed portion of the base region and the electrically conductive region, which operates as a trench-based electrode.

Claims

1-53. -53. (Cancelled)

54. A method of forming a vertical power device, comprising the steps of:

forming a plurality of trenches in a surface of a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent the surface;

lining the plurality of trenches with trench insulating layers;

forming electrically conductive regions on the trench insulating layers;

implanting transition region dopants of first conductivity type at a first dose level and first energy level into the drift region;

forming a gate electrode that extends opposite the implanted transition region dopants, on the surface;

implanting shielding region dopants of second conductivity type at a second dose level and second energy level into the surface, using the gate electrode as an implant mask;

implanting base region dopants of second conductivity type at a third dose level and third energy level into the surface, using the gate electrode as an implant mask;

driving the implanted transition, shielding and base region dopants into the substrate to define a transition region that extends in the drift region, first and second shielding regions that extend on opposite sides of the transition region and form respective P—

N rectifying junctions therewith and first and second base regions that extend on opposite sides of the transition region and form respective P—

N rectifying junctions therewith;

forming source regions of first conductivity type in the first and second base regions;

etching back portions of the trench insulating layers to expose the source, base and shielding regions; and

forming a source contact that ohmically contacts the exposed source, base and shielding regions and the electrically conductive regions.

55. The method of claim 54, wherein said step of implanting transition region dopants comprises implanting transition region dopants into the conductive regions within the plurality of trenches and into mesas defined between the plurality of trenches.

56. The method of claim 54, wherein the first and second energy levels are at respective levels that cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of a peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.

57. The method of claim 54, wherein the gate electrode is an insulated gate electrode;

wherein the transition region extends to an interface between the insulated gate electrode and the surface; and

wherein a peak first conductivity type dopant concentration in the transition region is greater than about ten times a surface dopant concentration in the transition region.

58. The method of claim 54, wherein the second dose level is greater than the third dose level;

and wherein the second energy level is greater than the third energy level.

59. A method of forming a vertical power device, comprising the steps of:

forming a trench in a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent a sidewall of the trench;

lining the trench with a trench insulating layer;

forming a trench-based electrode on the trench insulating layer;

forming an insulated gate electrode on a surface of the substrate;

forming a base region of second conductivity type that extends in the substrate and to the sidewall of the trench;

forming a source region of first conductivity type that extends in the base region and to the sidewall of the trench;

etching back a portion of the trench insulating layer to expose portions of the base and source regions that extend along the sidewall of the trench; and

forming a source contact that ohmically contacts the exposed portions of the base and source regions.

60. A method of forming a vertical power device, comprising the steps of:

forming a lateral-channel MOSFET having a base region of second conductivity type within the semiconductor substrate and a source region of first conductivity type within the base region;

forming a trench in the semiconductor substrate, said trench having sidewalls that define an interface with the base region;

lining the sidewalls of said trench with a trench insulating layer;

forming an electrically conductive region on the trench insulating layer;

removing an upper portion of the trench insulating layer to expose a portion of the base region extending along the interface; and

forming a source electrode ohmically contacting the source region, the exposed portion of the base region and the electrically conductive region.