Structure and method for forming a trench MOSFET having self-aligned features

• US 20040232481A1
• Filed: 05/20/2003
• Published: 11/25/2004
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean, Herrick, Robert, Losee, Becky
• Granted Patent: US 6,916,745 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

In accordance with an embodiment of the present invention, a semiconductor device is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.

Claims

1. A method of forming a semiconductor device, comprising:

defining an exposed surface area of a silicon layer where silicon can be removed;

removing a portion of the silicon layer to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer;

defining additional exposed surface areas of the silicon layer where silicon can be removed; and

removing additional portions of the silicon layer to form outer sections of the trench, the outer sections of the trench extending into the silicon layer from the additional exposed surface areas of the silicon layer, the middle section of the trench extending deeper into the silicon layer than the outer sections of the trench.

2. The method of claim 1 wherein the step of removing additional portions of the silicon layer shapes the sidewalls of the trench such that an upper portion of trench sidewalls fan out near the top of the trench to extend directly over a portion of the silicon layer adjacent each trench sidewall.

3. The method of claim 1 wherein:

the step of defining an exposed surface area of a silicon layer comprises forming and removing a portion of an insulating layer to define the exposed surface area of the silicon layer; and

the step of defining additional exposed surface areas of the silicon layer comprises isotropically etching remaining regions of the insulating layer to expose the additional surface areas of the silicon layer.

4. The method of claim 1 wherein the silicon layer comprises a body region, the method further comprising:

prior to forming the trench, implanting impurities to form a first region of a conductivity type opposite that of the body region along a surface of the body region such that after the trench is formed;

(i) the trench extends through the first region and the body region so as to divide each of the first region and the body region into two portions, and (ii) the two portions of the first region extend along surface areas of corresponding two portions of the body region and directly below the outer sections of the trench.

5. The method of claim 4 wherein the body region is an epitaxial layer.

6. The method of claim 4 wherein the silicon layer comprises an epitaxial layer, the method further comprising:

implanting impurities to form the body region in the epitaxial layer, the body region having a conductivity type opposite that of the epitaxial layer.

7. The method of claim 1 further comprising:

forming a gate electrode partially filling the trench to below the outer sections of the trench.

8. The method of claim 7 wherein the step of forming a gate electrode comprises:

forming a gate insulator extending at least along the trench sidewalls;

depositing polysilicon; and

etching back the polysilicon so that the polysilicon partially fills the trench to below the outer sections of the trench.

9. The method of claim 7 wherein the silicon layer comprises a body region, the method further comprising:

implanting impurities to form a first region in the body region, the first region extending along a surface of the body region and directly below the outer sections of the trench.

10. The method of claim 9 further comprising:

forming the body region prior to forming the trenches.

11. The method of claim 9 wherein the body region is an epitaxial layer, and the trench extends through the body region.

12. The method of claim 9 wherein:

the silicon layer comprises an epitaxial layer extending over a substrate, the body region being in the epitaxial layer, and

the epitaxial layer, the substrate, and the first region have a conductivity type opposite that of the body region.

13. The method of claim 9 further comprising:

forming a dielectric layer extending only across a top surface of the trench; and

removing exposed silicon until;

(i) of the first region, only portions located substantially directly below the outer sections of the trench remain, the remaining portions of the first region forming source regions of the semiconductor device, and (ii) a surface area of the body region becomes exposed.

14. The method of claim 13 wherein the exposed silicon removing step exposes a sidewall of the dielectric layer, the sidewall of the dielectric layer together with an exposed sidewall of each source region forming a sidewall of a contact opening for contacting the body region and source region.

15. The method of claim 13 wherein the step of forming a dielectric layer comprises:

forming a dielectric layer extending over the trench and the body region, the dielectric layer substantially filling a remaining portion of the trench over the gate electrode;

performing a dielectric flow to planarize the top surface of the dielectric layer; and

uniformly etching the dielectric layer until silicon is reached, wherein upon reaching silicon;

(i) only a portion of the dielectric layer extending across the top surface of the trench remains, and (ii) a surface area of the first region is exposed.

16. The method of claim 13 further comprising:

forming a highly doped region of the same conductivity type as the body region along the exposed surface area of the body region; and

forming a metal layer to contact the highly doped region and the source regions.

17. A method of forming a trench MOSFET, comprising:

forming a first insulating layer over a silicon layer;

removing predefined portions of the first insulating layer to define isolated exposed surface areas of the silicon layer;

performing a first silicon etch to form a middle section of each of a plurality of trenches extending into the silicon layer from the isolated exposed surface areas of the silicon layer;

isotropically etching remaining regions of the first insulating layer to expose additional surface areas of the silicon layer; and

performing a second silicon etch to form outer sections of each trench, the outer sections of the trenches extending into the silicon layer from the additional exposed surface areas of the silicon layer, the middle section of each trench extending deeper into the silicon layer than its outer sections.

18. The method of claim 17 wherein the isotropically etching step shapes the sidewalls of each trench such that an upper portion of the trench sidewalls fan out near the top of the trench to extend directly over a portion of the silicon layer adjacent each trench sidewall.

19. The method of claim 17 further comprising:

forming a gate insulator extending at least along the sidewalls of each trench; and

forming a polysilicon layer partially filling each trench to below the outer sections of each trench.

20. The method of claim 19 wherein the silicon layer comprises an epitaxial layer in which the trench is formed, the method further comprising:

implanting impurities to form body regions of opposite conductivity type to that of the epitaxial layer in the epitaxial layer between adjacent trenches; and

implanting impurities to form a first region of opposite conductivity type to that of the body regions in each body region, each first region extending along a surface of a corresponding body region and directly below the outer sections of adjacent trenches.

21. The method of claim 20 further comprising:

forming a substantially planar surface using a second insulating layer such that a surface area of each first region is exposed while the second insulating layer substantially fills a remaining portion of each trench over the corresponding gate electrode; and

removing exposed silicon until;

(i) of each first region, only portions located substantially directly below the outer sections of adjacent trenches remain, the remaining portions of the first region forming source regions of the MOSFET, and (ii) a surface area of each body region becomes exposed.

22. The method of claim 21 wherein the exposed silicon removing step exposes a sidewall of the second insulating layer in each trench such the sidewall of the second insulating layer in each trench together with exposed sidewalls of source regions form contact openings between every two adjacent trenches, the method further comprising:

forming a metal layer to contact the exposed surface area of each body region and the exposed sidewalls of the source regions through the contact openings.

23. The method of claim 21 wherein the step of forming a substantially planar surface comprises:

forming a second insulating layer extending over the trenches and the body regions, the second insulating layer substantially filling a remaining portion of each trench over the corresponding gate electrode;

performing a dielectric flow to planarize the top surface of the second insulating layer; and

uniformly etching the dielectric layer until silicon is reached, wherein upon reaching silicon;

(i) only portions of the second insulating layer extending across the top surface of each trench remain, and (ii) a surface area of each first region is exposed.

24. A method of forming a semiconductor device, comprising:

forming a masking layer over a silicon layer, the masking layer having an opening through which a surface area of the silicon layer is exposed;

isotropically etching the silicon layer through the masking layer opening so as to remove a bowl-shaped portion of the silicon layer, the bowl-shaped portion having a middle portion along the exposed surface area of the silicon layer and outer portions extending directly underneath the masking layer, wherein the outer portions of the removed silicon layer extending directly underneath the masking layer form outer sections of a trench; and

removing additional portions of the silicon layer through the masking layer opening so as to form a middle section of the trench which extends deeper into the silicon layer than the outer sections of the trench.

25. The method of claim 24 wherein the silicon layer comprises a body region, the method further comprising:

forming a gate electrode partially filling the trench;

forming an insulating layer substantially filling a remaining portion of the trench over the gate electrode;

removing exposed silicon adjacent the trench such that;

(i) an edge of the insulating layer in the trench becomes exposed, the edge of the insulating layer forming a sidewall of a contact opening; and

(ii) a surface area of the body region becomes exposed; and

forming a metal layer contacting the exposed surface areas of the body region through the contact opening.

26. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming an insulating layer filling an upper portion of each trench; and

removing exposed silicon from adjacent the trenches to expose an edge of the insulating layer in each trench, the exposed edge of the insulating layer in each trench defining a portion of each contact opening formed between every two adjacent trenches.

27. The method of claim 26 further comprising:

prior to removing exposed silicon, forming a first region of a first conductivity type in the silicon layer so that after said exposed silicon removing step, of the first region, only a portion adjacent each trench sidewall remains, the remaining portion of the first region adjacent each trench sidewall forming a source region of the semiconductor device,

wherein the step of removing exposed silicon further exposes a sidewall of each source region such that the exposed edge of the insulating layer in each trench together with the exposed sidewall of a corresponding source region form one sidewall of a contact opening between every two adjacent trenches.

28. The method of claim 26 further comprising:

forming a gate electrode filling a lower portion of each trench, the insulating layer substantially filling a remaining portion of each trench.

29. A method of forming a semiconductor device, comprising:

forming a plurality of trenches in a silicon layer;

forming a first region along a surface of the silicon layer;

forming an insulating layer fully contained within each trench, the insulating layer in each trench extending directly over a portion of the first region adjacent each trench sidewall; and

removing exposed silicon from adjacent each trench until, of the first region, only the portions adjacent the trench sidewalls remain, the remaining portions of the first region adjacent the trench sidewalls forming source regions which are self-aligned to the trenches.

30. A method of forming a semiconductor device, comprising:

removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and

forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.

31. A method of forming a semiconductor device, comprising:

removing portions of a silicon layer such that a plurality of trenches are formed each having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer adjacent each trench sidewall;

forming a gate electrode partially filling each trench;

forming an insulating layer in each trench, the insulating layer extending over each gate electrode and over the portions of the silicon layer which extend directly under the trench sidewalls; and

removing exposed silicon to expose an edge of the insulating layer in each trench, the exposed edge of the insulating layer in each trench defining a portion of each contact opening formed between every two adjacent trenches.

32. The method of claim 31 further comprising:

forming a first region of a first conductivity type in the silicon layer, wherein the step of removing exposed silicon removes portions of the first region such that of the first region only portions adjacent each trench sidewall remain, the remaining portions of the first region adjacent each trench sidewall forming a source region of the semiconductor device.

33. A semiconductor device comprising:

a trench in a silicon layer; and

a source region formed in the silicon layer adjacent each sidewall of the trench, wherein the trench sidewalls are shaped along the silicon layer such that the trench sidewalls fan out near the top of the trench to extend directly over a substantial portion of each source region.

34. The semiconductor device of claim 33 further comprising:

a gate electrode partially filling the trench but overlapping each source region along the trench sidewalls; and

an insulating layer substantially filling a remaining portion of the trench over the gate electrode, wherein a sidewall of the insulating layer in the trench together with a sidewall of a corresponding source region form a sidewall of a contact opening through which contact is made at least with the source region.

35. The semiconductor device of claim 34 further comprising:

a body region adjacent each trench sidewall, the body regions being of opposite conductivity type to that of the source regions; and

a metal layer contacting the body regions and the source regions through the contact opening.

36. The semiconductor device of claim 33 wherein the insulating layer is fully contained within the trench.

37. A trench MOSFET comprising:

a plurality of trenches formed in silicon layer such that sidewalls of each trench along the silicon layer fan out near the top of the trench to extend directly over a portion of the silicon layer;

a gate electrode partially filling each trench;

an insulating layer substantially filling a remaining portion of each trench, the insulating layer in each trench being fully contained within the trench;

a plurality of body regions in the silicon layer, each body region extending between two adjacent trenches; and

a source region formed adjacent each trench sidewall in the body regions such that the insulating layer extends directly over at least a portion of each source region, the source regions being of opposite conductivity type to the body regions.

38. The trench MOSFET of claim 37 wherein sidewalls of the insulating layer in each trench together with corresponding sidewalls of the source regions form a contact opening between every two adjacent trenches.

39. The trench MOSFET of claim 38 further comprising:

a metal layer contacting the body region and the source regions through the contact openings.

40. The trench MOSFET of claim 37 wherein the gate electrode in each trench overlaps corresponding source regions but is recessed below the portion of the trench sidewalls where the trench sidewalls start to fan out.

41. The trench MOSFET of claim 37 wherein:

the silicon layer further comprises an epitaxial layer extending over a substrate, the body regions being formed in the epitaxial layer, and

the substrate, the epitaxial layer, and the source regions have a conductivity type opposite that of the body regions.

42. A semiconductor device comprising:

a plurality of trenches in a silicon layer;

an insulating layer filling an upper portion of each trench, the insulating layer being contained within each trench; and

a source region formed in the silicon layer adjacent each trench sidewall such that a sidewall of the insulating layer in each trench together with a sidewall of a corresponding source region form a contact opening between every two adjacent trenches.

43. The semiconductor device of claim 42 wherein the insulating layer in each trench extends over a substantial portion of corresponding source regions, the semiconductor device further comprising:

a metal layer contacting at least the source regions through the contact openings.