High aspect ratio contact surfaces having reduced contaminants

• US 20040232547A1
• Filed: 02/27/2004
• Published: 11/25/2004
• Est. Priority Date: 08/31/2000
• Status: Abandoned Application

• Current Assignee: Doug Hahn, Kelly Williamson, Larry Hillyer, Steve Byrne
• Original Assignee: Doug Hahn, Kelly Williamson, Larry Hillyer, Steve Byrne
• Inventors: Hillyer, Larry, Hahn, Doug, Williamson, Kelly, Byrne, Steve
• Application Number:
  US10/787,125
• Publication Number:
  US 20040232547A1
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Abstract

Contact openings in semiconductor substrates are formed through insulative layers using an etchant material. The etchant typically leaves behind a layer of etch residue which interferes with the subsequent deposition of conductive material in the opening, as well as the conductive performance of the resulting contact. A method of etch removal from semiconductor contact openings utilizes ammonia to clean the surfaces thereof of any etch residue.

Claims

1-44. -44. (Cancelled)

45. A semiconductor device comprising:

an insulating layer;

an ammonia-cleaned, etched opening in said insulating layer; and

a conductor in said ammonia-cleaned, etched opening.

46. An integrated circuit comprising:

an ammonia-cleaned, etch residue-free High Aspect Ratio opening provided in an insulating layer, said opening being formed over a polysilicon region; and

a conductor within said opening, said conductor being electrically connected with said polysilicon region.

47. An integrated circuit as in claim 46 further comprising a silicide layer between said conductor and said polysilicon region.

48. An integrated circuit as in claim 46, wherein said integrated circuit is a memory circuit.

49. An integrated circuit as in claim 47 wherein the interface area between said conductor and polysilicon region is free of oxygen contamination.

50-53. -53. (Cancelled)