Method for adaptively testing integrated circuits based on parametric fabrication data

• US 20040236531A1
• Filed: 05/19/2003
• Published: 11/25/2004
• Est. Priority Date: 05/19/2003
• Status: Abandoned Application

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Madge, Robert
• Application Number:
  US10/441,882
• Publication Number:
  US 20040236531A1
• Time in Patent Office: Days
• US Class Current: 702/118
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12

Abstract

A method of adaptively testing electronic circuits based on fabrication data includes steps for receiving as input fabrication data of the electronic circuits from at least one of electrical test and in-line inspection; calculating a process capability from the fabrication data; and selecting a test selection program based on the process capability to minimize testing cost and to verify performance specifications.

Claims

1. A method of adaptively testing electronic circuits based on fabrication data comprising steps for:

(a) receiving as input fabrication data of the electronic circuits from at least one of electrical test and in-line inspection;

(b) calculating a process capability from the fabrication data; and

(c) selecting a test selection program based on the process capability to minimize testing cost and to verify performance specifications.

2. The method of claim 1 wherein step (a) further includes receiving at least one of Cp, Cpk, Vtn, Vtp, Vtn/Vtp, metal resistance, via resistance, and percentage of failed via chains.

3. The method of claim 1 wherein step (b) further includes measuring a standard deviation of a parameter with respect to a specifications window.

4. The method of claim 1 wherein step (b) further includes calculating the process capability as a function of at least one of a wafer, a number of wafers, and a time period.

5. The method of claim 1 wherein step (c) further includes selecting the test program to exercise selected features of a specific product.

6. The method of claim 1 wherein step (c) further includes selecting the test program from a range of options including at least one of full testing, defect testing, low pin-count testing, structural testing, mixed signal testing, I/O testing, at-speed testing, delay fault testing, built-in self testing, IDDQ testing, memory testing, and reduced vector testing.

7. A computer program product for adaptively testing electronic circuits based on fabrication data comprising:

a medium for embodying a computer program for input to a computer; and

a computer program embodied in the medium for causing the computer to perform the following functions;

(a) receiving as input fabrication data of the electronic circuits from at least one of electrical test and in-line inspection;

(b) calculating a process capability from the fabrication data; and

(c) selecting a test selection program based on the process capability to minimize testing cost and to verify performance specifications.

8. The computer program product of claim 7 wherein function (a) further includes receiving at least one of Cp, Cpk, Vtn, Vtp, Vtn/Vtp, metal resistance, via resistance, and percentage of failed via chains.

9. The computer program product of claim 7 wherein function (b) further includes measuring a standard deviation of a parameter with respect to a specifications window.

10. The computer program product of claim 7 wherein function (b) further includes calculating the process capability as a function of at least one of a wafer, a number of wafers, and a time period.

11. The computer program product of claim 7 wherein function (c) further includes selecting the test program to exercise selected features of a specific product.

12. The computer program product of claim 7 wherein function (c) further includes selecting the test program from a range of options including at least one of full testing, defect testing, low pin-count testing, and structural testing.