Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
First Claim
1. A computer system comprising:
- at least one dense logic device;
a controller for coupling said at least one dense logic device to a control block and a memory bus;
one or more memory module slots coupled to said memory bus, at least one of said one or more memory module slots comprising a buffered memory module;
an adapter port associated with a subset of said one or more memory module slots, said adapter port including associated memory resources; and
at least one direct execution logic element coupled to said adapter port, said memory resources being selectively accessible by said at least one dense logic device and said at least one direct execution logic element.
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Accused Products
Abstract
An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (“MAP®”, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP® elements, common memory boards and the like.
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Citations
76 Claims
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1. A computer system comprising:
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at least one dense logic device;
a controller for coupling said at least one dense logic device to a control block and a memory bus;
one or more memory module slots coupled to said memory bus, at least one of said one or more memory module slots comprising a buffered memory module;
an adapter port associated with a subset of said one or more memory module slots, said adapter port including associated memory resources; and
at least one direct execution logic element coupled to said adapter port, said memory resources being selectively accessible by said at least one dense logic device and said at least one direct execution logic element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A computer system comprising:
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at least one dense logic device;
an interleaved controller for coupling said at least one dense logic device to a control block and a memory bus;
a plurality of memory slots coupled to said memory bus, at least one of said plurality of memory slots comprising a buffered memory module;
an adapter port associated with at least two of said plurality of memory slots, each of said adapter port including associated memory resources; and
a direct execution logic element coupled to at least one of said adapter ports, said memory resources being selectively accessible by said at least one dense logic device and said direct execution logic element. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A computer system including an adapter port for electrical coupling between a memory bus of said computer system and a network interface, said computer system comprising at least one dense logic device coupled to said memory bus through a memory module connector, said adapter port comprising:
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a memory resource associated with said adapter port; and
a control block for selectively enabling access by said at least one dense logic device to said memory resource. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76)
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Specification
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- Resources
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Current AssigneeSRC Computers, Inc.
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Original AssigneeSRC Computers, Inc.
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InventorsBurton, Lee A.
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Application NumberUS10/869,199Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current710/22CPC Class CodesG06F 13/1668 Details of memory controllerG06F 13/385 for adaptation of a particu...
