Bus arbiter and bus arbitrating method

• US 20040236889A1
• Filed: 01/07/2004
• Published: 11/25/2004
• Est. Priority Date: 05/24/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Young-Sik
• Granted Patent: US 7,099,976 B2
• Time in Patent Office: Days
• US Class Current: 710/113
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

Provided are a bus arbiter and a bus arbitrating method. The bus arbiter comprises a bus request register file, a bank register file, and a comparing circuit, thereby preferentially assigning a bus grant signal to a bus master causing a page hit among a plurality of bus masters outputting bus request signals. The bus request register file stores each of the memory access address output from corresponding bus master. The bank register file stores a page index stored in a sense amplifier of corresponding memory bank of an external memory device. The comparing circuit compares a page index stored in a register of a bank register file selected based on corresponding memory access address with a page index stored in the bus request register file and then outputs a page hit or page miss to the bus request register file according to the comparison result. The bus arbiter preferentially assigns a bus grant signal granting access to the bus to a bus master causing the page hit.

Claims

1. A bus arbiter for outputting a bus grant signal to a bus master granted access to a bus based on bus request signals and memory access addresses, each of which is output from respective M bus masters connected to the bus, the bus arbiter comprising;

a bus request register file comprising M registers, each of the M registers for storing each of the memory access addresses output from a corresponding bus master;

a bank register file comprising N registers, each of the N registers for storing a page index stored in a sense amplifier of a corresponding memory bank of an external memory device; and

a comparing circuit comprising M comparators, each of the M comparators for comparing a page index stored in a register of the bank register file selected based on a corresponding memory access address with a page index stored in each of the M registers of the bus request register file and outputting a page HIT or page MISS to each of the M registers of the bus request register file according to the comparison result,

wherein the bus arbiter preferentially grants a bus master causing the page HIT access to the bus.

2. The bus arbiter of claim 1, wherein the bus arbiter assigns a bus grant signal to a bus master causing the page MISS according to a fairness scheme.

3. The bus arbiter of claim 1, wherein each of the memory access addresses comprises a page index field that stores a page index and a bank index field that stores a bank index.

4. The bus arbiter of claim 1, wherein each of the M registers comprises a page index field for storing a page index, a bank index field for storing a bank index, and a page HIT/page MISS field for storing information about the page HIT and/or the page MISS.

5. A bus arbiter for outputting a bus grant signal to a bus master granted access to a bus based on bus request signals and memory access addresses, each of which is output from respective M bus masters connected to the bus, the bus arbiter comprising;

a request register file comprising M registers;

a bank register file comprising N registers; and

a comparing circuit comprising M comparators,

wherein each of the M registers comprises a page index field for storing a page index output from a corresponding bus master and a bank index for storing a bank index output from the corresponding bus master,

each of the N registers comprises an open page index field that stores a page index stored in a sense amplifier of a memory bank of an external memory device,

each of the M comparators for comparing a page index stored in an index page field of each of the M registers with an open page index stored in a register of the bank register file selected based on a bank index stored in a bank index field of each of the M registers and outputting the comparison result to a page HIT/page MISS field of each of the M registers,

wherein the bus arbiter preferentially grants a bus master causing the page HIT access to the bus.

6. The bus arbiter of claim 5, wherein the bus arbiter assigns a bus grant signal to a bus master causing the page MISS according to a fairness scheme.

7. A bus arbitrating method by which a bus grant signal is output to a bus master granted access to a bus based on bus request signals and memory access addresses, each of which is output from a plurality of bus masters connected to the bus, the bus arbitrating method comprising;

storing a page index and a bank index, included in each of the memory access addresses, in a corresponding register of a bus request register file;

storing a corresponding open page index and searching for a register corresponding to the bank index;

comparing the page index with the open page index and storing a page HIT/page MISS in the corresponding register of the bus request register file according to the comparison result; and

assigning, preferentially, a bus grant signal granting access to the bus to a bus master causing the page HIT.

8. The bus arbitrating method of claim 7, further comprising assigning a bus grant signal to a bus master causing the page MISS according to a fairness scheme.