Processor book for building large scalable processor systems
First Claim
1. A processor book comprising:
- a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S0 and T0;
a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S1 and T1;
a third set of buses external to said first processor chip module and said second processor chip module and which respectively connect each processor chip of the first processor chip module to a corresponding processor chip of the second processor chip module, wherein S0 connects to S1, and T0, connects to T1; and
means for providing each of said processor chips with an external connection point by way of an external bus, said means including a plurality of external routing buses each connected to a respective processor chip in said processor book.
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Abstract
A method and system for providing a multiprocessor processor book that is utilized as a building block for a large scale data processing system. Two 4-way multi-chip modules (MCM) are utilized to create the processor book. The first and second MCMs are configured with normal wiring among their respective processors. An additional wiring is provided that links external buses of each chip of the first MCM with buses of a corresponding chip of the second MCM and vice versa. The additional wiring enables each processor of the first MCM substantially direct access to the distributed memory components of the next MCM with no affinity. The processor book is plugged into a processor rack configured to receive multiple processor books that together make up the large scale data processing system.
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Citations
22 Claims
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1. A processor book comprising:
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a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S0 and T0;
a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S1 and T1;
a third set of buses external to said first processor chip module and said second processor chip module and which respectively connect each processor chip of the first processor chip module to a corresponding processor chip of the second processor chip module, wherein S0 connects to S1, and T0, connects to T1; and
means for providing each of said processor chips with an external connection point by way of an external bus, said means including a plurality of external routing buses each connected to a respective processor chip in said processor book. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 16)
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9. A data processing system comprising:
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a processor book with an external connection point, said processor book including;
a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S0 and T0;
a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S1 and T1;
a third set of buses external to said first processor chip module and said second processor chip module and which interconnect each of processor chips S0 andT0, U0, and V0 to a respective one of processor chips S1, and T1;
a fourth set of buses extending externally from said processor book, said fourth set of buses including a plurality of external routing buses each connected to a respective processor chip in said processor book, wherein said external routing buses provide a connection point for components external to the processor book; and
components external to said processor book that are coupled to said processor book via said external connection point. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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17. A data processing system comprising:
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a processor rack including a backplane with a plurality of connectors for receiving a plug-in head of processor books, wherein each connector of said plurality of connectors are wired sequentially to each other; and
a first processor book having said plug-in head coupled to a first one of said plurality of connectors, said processor book comprising;
a first processor chip module including a first plurality of processor chips interconnected by a first set of intra-module buses that are internal to said first processor chip module, said first plurality of processor chips including at least processor chips S0 and T0;
a second processor chip module including a second plurality of processor chips interconnected by a second set of intra-module buses that are internal to said second processor chip module, said second plurality of processor chips including processor chips S1 and T1;
a third set of buses external to said first processor chip module and said second processor chip module and which interconnect each of processor chips S0 andT0, U0, and V0 to a respective one of processor chips S1, and T1; and
a fourth set of buses extending externally from said processor book, said fourth set of buses including a plurality of external routing buses each connected to a respective processor chip in said processor book, wherein said external routing buses provide a connection point for components external to the processor book. - View Dependent Claims (18, 19, 20, 21)
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22. The data processing system of claim 22, further comprising:
wiring means for completing a connection from one connector to another when said connector does not contain a processor book coupled thereto so that a complete connection path is always provided within said processor rack.
Specification