Simplified memory detection

• US 20040236933A1
• Filed: 05/20/2003
• Published: 11/25/2004
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Dewey, Thomas E.
• Granted Patent: US 7,159,104 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: H01R 13/7039 the coupling part with coding means activating the switch to establish different circuits

Abstract

Automatic recognition of the type of memory within a device package by using strap resistors within the device package. Such recognition enables a processor, such as a GPU, to automatically configure itself to work with the memory. A device package includes a strap contact and a bit input that are electrically connected. The device package beneficially contains a processor (such a GPU) that is operatively connected to the bit input, and a memory device that is operatively connected to the processor. By selectively inserting a strap resistor the voltage applied to the bit input changes state. That state can be read and used to set up the system.

Claims

1. A device package having a strap contact and a bit input, said package containing a processor that is operatively connected to the bit input, a memory device that is operatively connected to said processor, and an internal contact that is operatively connected to said strap contact;

wherein the presence of a strap resistor within the device package that is connected to said internal contact is for setting a first voltage on said bit input;

wherein the absence of a strap resistance is for setting a second voltage on said bit input;

wherein the first voltage controls the operation of the processor in a first manner; and

wherein the second voltage controls the operation of the processor in a second manner.

2. The device of claim 1 wherein the presence of a strap resistor signals a specific characteristic of the memory device.

3. The device of claim 1 wherein the strap resistor is a low resistance element.

4. The device of claim 4 wherein the strap resistor is a conductive ball.

5. A computer system comprising:

a wiring board having a board contact that is resistively coupled to a voltage source;

a device package attached to said wiring board and containing a graphic processor, wherein said device package includes a strap contact that is electrically coupled to said board contact, and a bit input that is resistively coupled to said strap contact;

wherein the presence of a strap resistor within the device package that is connected to said strap contact sets a first voltage on said bit input;

wherein the absence of a strap resistor within the device package sets a second voltage on said bit input;

wherein the first voltage controls the operation of the graphic processor in a first manner; and

wherein the second voltage controls the operation of the graphic processor in a second manner.

6. The computer system of claim 5 wherein the device package further contains a memory device that is operatively connected to said graphic processor.

7. The computer system of claim 6 wherein the first voltage signals that a first type of memory device is contained in the device package, and wherein the second voltage signals that a second type of memory is contained in the device package.

8. The computer system of claim 5 wherein the strap resistor is a low resistance element.

9. The computer system of claim 8 wherein the strap resistor is a conductive ball.

10. The computer system of claim 8 wherein the strap resistor is a fuse-able interconnect in the device package.

11. The computer system of claim 5 wherein the voltage source is the system'"'"'s power supply voltage.

12. The computer system of claim 5 wherein the voltage source is the system'"'"'s ground.

13. The computer system of claim 5 wherein the wiring board includes a first resistor coupled between a power supply and the strap contact.

14. The computer system of claim 5 wherein the wiring board includes a first resistor coupled between ground and the strap contact.

15. The computer system of claim 13 wherein the wiring board includes a second resistor coupled between the strap contact and the bit input.

16. The computer system of claim 14 wherein the wiring board includes a second resistor coupled between the strap contact and the bit input.

17. A method of operating a computer system comprising:

installing a device package containing a processor and memory that is connected to the processor on a wiring board, wherein the device package includes strap resistors that identify the type of memory;

configuring the wiring board such that the strap resistors cause a bit pattern on bit inputs to the device package, wherein the bit pattern depends on the strap resistors;

reading the bit pattern;

identifying the memory type from the bit pattern; and

configuring the processor to work with the memory.

18. The method of claim 17 wherein a strap resistor is a low resistance element.

19. The method of claim 18 wherein the strap resistor is a conductive ball.

20. The method of claim 18 wherein the strap resistor is a fuse-able interconnect in the device package.

21. A computing system comprising:

a host processor;

a host memory, the host memory storing programs for the host processor;

a system interface configured to interface with the host processor; and

a MAP configured to interface with the system interface including;

a memory device; and

one or more strap resistors that identify characteristics of the memory device.

22. The computing system of claim 21, wherein the characteristics include at least one of memory device speed, memory device operating voltage, and memory device capacity.

23. The computing system of claim 21, wherein the host memory is configured to interface with the system interface.

24. The computing system of claim 21, wherein the host memory is configured to directly interface with the host processor.