Soft errors handling in EEPROM devices

• US 20040237010A1
• Filed: 06/22/2004
• Published: 11/25/2004
• Est. Priority Date: 05/20/1992
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Daniel C. Guterman, Daniel L. Auclair, Jeffrey Craig, John S. Mangan, Robert D. Norman, Sanjay Mehrotra
• Inventors: Mangan, John S., Mehrotra, Sanjay, Guterman, Daniel C., Craig, Jeffrey, Norman, Robert D., Auclair, Daniel L.
• Granted Patent: US 7,548,461 B2
• Time in Patent Office: Days
• US Class Current: 714/721
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Claims

1-34. -34. (Canceled)

35. A method comprising:

sensing a read current in a flash cell in a flash memory device;

comparing the read current with a high reference current;

comparing the read current with a low reference current; and

initiating an operation on the flash cell if the read current is between the low reference current and the high reference current.

36. A method comprising:

reading a flash cell in a flash memory device to generate a read signal;

comparing the read signal with a low signal;

comparing the read signal with a high signal; and

initiating an operation on the flash cell if the read signal is between the low signal and the high signal.

37. A method comprising:

sensing a read current in a flash cell in a flash memory device;

comparing the read current with a high reference current;

comparing the read current with a low reference current;

identifying data stored in the flash cell based on the comparisons; and

initiating an operation on the flash cell if the read current is between the low reference current and the high reference current.

38. A method comprising:

reading a flash cell in a flash memory device to generate a read signal;

comparing the read signal with a low signal;

comparing the read signal with a high signal;

identifying data stored in the flash cell based on the comparisons; and

initiating an operation on the flash cell if the read signal is between the low signal and the high signal.

39. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

sensing a read current in a flash cell in the flash memory device;

comparing the read current with a high reference current;

comparing the read current with a low reference current; and

initiating an operation on the flash cell if the read current is between the low reference current and the high reference current.

40. The method of claim 39 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.

41. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

reading a flash cell in the flash memory device to generate a read signal;

comparing the read signal with a low signal;

comparing the read signal with a high signal; and

initiating an operation on the flash cell if the read signal is between the low signal and the high signal.

42. The method of claim 41 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.

43. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

sensing a read current in a flash cell in the flash memory device;

comparing the read current with a high reference current;

comparing the read current with a low reference current;

identifying data stored in the flash cell based on the comparisons; and

initiating an operation on the flash cell if the read current is between the low reference current and the high reference current.

44. The method of claim 43 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.

45. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

reading a flash cell in the flash memory device to generate a read signal;

comparing the read signal with a low signal;

comparing the read signal with a high signal;

identifying data stored in the flash cell based on the comparisons; and

initiating an operation on the flash cell if the read signal is between the low signal and the high signal.

46. The method of claim 45 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.

47. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

reading a flash cell in a read cycle in the flash memory device to generate a read signal;

comparing the read signal with a first reference signal in the read cycle to indicate data stored in the flash cell; and

comparing the read signal with a second reference signal in the read cycle to indicate if the flash cell is leaky.

48. The method of claim 47 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.

49. A method of operating a system comprising:

exchanging signals between a memory controller and a flash memory device;

reading a flash cell in a read cycle in the flash memory device to generate a read signal;

generating a plurality of reference signals;

comparing the read signal with each of the reference signals in the read cycle;

generating a data signal based on the comparison to indicate data stored in the flash cell; and

generating a refresh signal based on the comparison to request a refresh of the flash cell if the flash cell is leaky.

50. The method of claim 49 wherein exchanging signals further comprises exchanging signals between a processor or a microprocessor and a flash memory device embedded in a single integrated circuit chip.