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Dual decode scheme

  • US 20040237018A1
  • Filed: 05/23/2003
  • Published: 11/25/2004
  • Est. Priority Date: 05/23/2003
  • Status: Active Grant
First Claim
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1. An interface for a device adapted to couple to an interconnect, comprising:

  • decode and error check logic that receives error check bits and a target address from said interconnect and determines whether the target address was received in error; and

    a plurality of decode logic units that each receive the target address;

    wherein at least one of said decode logic units also receives the error check bits and corrects the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

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