Dual decode scheme

• US 20040237018A1
• Filed: 05/23/2003
• Published: 11/25/2004
• Est. Priority Date: 05/23/2003
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Riley, Dwight D.
• Granted Patent: US 7,877,647 B2
• Time in Patent Office: Days
• US Class Current: 714/753
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Abstract

As disclosed herein, an interface for a device adapted to couple to an interconnect may comprise decode and error check logic and a plurality of decode logic units. The decode and error check logic may receive error check bits and a target address from the interconnect and may determine whether the target address was received in error. At least one of the decode logic units also may receive the error check bits and correct the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

Claims

1. An interface for a device adapted to couple to an interconnect, comprising:

decode and error check logic that receives error check bits and a target address from said interconnect and determines whether the target address was received in error; and

a plurality of decode logic units that each receive the target address;

wherein at least one of said decode logic units also receives the error check bits and corrects the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

2. The interface of claim 1 further comprising a multiplexer controlled by logic coupled to said decode and error check logic that asserts a control signal to the multiplexer, wherein the multiplexer includes a plurality of inputs that are output signals from the plurality of decode logic units.

3. The interface of claim 1 wherein the at least one decode logic unit begins to correct the address before being informed whether the address is actually in error.

4. The interface of claim 1 wherein the at least one decode logic unit is informed that the address is in error after the at least one decode logic unit has completed correcting the address.

5. The interface of claim 1 wherein the plurality of decode logic units comprise two decode logic unit, one decode logic being the at least one decode logic that corrects the target address in parallel with the decode and error check logic determining whether the target address was received in error, and the other decode logic unit decodes the target address without correcting said target address.

6. The interface of claim 1 wherein the interconnect is PCI-X compliant.

7. An electronic system, comprising:

a CPU;

a bridge coupled to said CPU; and

a device coupled to said bridge, said device receiving transactions having

a target address, said device further comprising;

decode and error check logic that receives error check bits and a target address from said interconnect and determines whether the target address was received in error; and

a plurality of decode logic units that each receive the target address;

wherein at least one of said decode logic units also receives the error check bits and corrects the target address using the error check bits concurrently with the decode and error check logic determining whether the target address was received in error.

8. The system of claim 7 wherein the device further comprises selection logic controlled by logic coupled to said decode and error check logic that asserts a control signal to the selection logic, wherein the selection logic includes a plurality of input signals that are output signals received from the plurality of decode logic units.

9. The system of claim 7 wherein the at least one decode logic unit begins to correct the address before the decode and error check logic determines whether the address is in error.

10. The system of claim 7 wherein the at least one decode logic unit is alerted that the address is in error after the at least one decode logic unit completes correcting the address.

11. The system of claim 7 wherein the plurality of decode logic units comprise two decode logic units, one decode logic being the at least one decode logic that corrects the target address concurrently with the decode and error check logic determining whether the target address was received in error, and the other decode logic unit decodes the target address without correcting said target address.

12. An interface for a PCI-X compliant interconnect device, comprising:

decode and error check logic that receives error check bits and a target address from said interconnect and determines whether the target address was receive in error; and

a means for decoding the target address concurrently with said decode and error check logic determining whether the target address was received in error.

13. The interface of claim 12 wherein the means includes a means for beginning to correct the address before being informed whether the address is actually in error.

14. The interface of claim 12 wherein the means includes a means for completing correcting the address before being informed that the address is in error.

15. A method of determining whether a transaction comprising a target address and error check bits targets a device, comprising:

determining whether the target address has an error;

while determining whether the target address has an error, correcting the target address to produce a corrected address and decoding said corrected address; and

while determining whether the target address has an error and correcting the target address, decoding said target address without correcting said target address.

16. The method of claim 15 further including asserting a signal indicating that the target address has an error, and correcting the target address completes before said signal is asserted.