Thin film transistor array panel and liquid crystal display including the panel

• US 20040238823A1
• Filed: 05/28/2004
• Published: 12/02/2004
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Chang, Hak-Sun, Kim, Tae-Hwan, Han, Eun-Hee
• Granted Patent: US 7,009,206 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A thin film transistor array panel is provided, which includes: a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes; a first insulating layer on the gate line; a semiconductor layer formed on the first insulating layer; a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas; a plurality of drain electrodes separated from the data lines; a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes; a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced apart from an edge of the pixel electrodes and substantially parallel to the edge of the pixel electrodes.

Claims

1. A thin film transistor array panel comprising:

a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes;

a first insulating layer on the gate line;

a semiconductor layer formed on the first insulating layer;

a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas;

a plurality of drain electrodes separated from the data lines;

a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes;

a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and

a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced apart from an edge of the pixel electrodes and substantially parallel to the edge of the pixel electrodes.

2. The thin film transistor array panel of claim 1, wherein the gate lines are curved near boundaries of the pixel areas.

3. The thin film transistor array panel of claim 1, wherein the common electrodes and the pixel electrodes extend substantially parallel to the oblique portions of the gate lines.

4. The thin film transistor array panel of claim 1, further comprising a plurality of storage electrode lines having a plurality of first portions extending substantially parallel to the data lines.

5. The thin film transistor array panel of claim 4, further comprising a plurality of signal lines overlapping the storage electrode lines to form storage capacitors.

6. The thin film transistor array panel of claim 1, wherein the pixel electrodes and the common electrodes comprises transparent material.

7. The thin film transistor array panel of claim 1, further comprising a plurality of color filters disposed under the passivation layer and in the pixel areas.

8. A liquid crystal display comprising:

a first panel;

a second panel facing the first panel; and

a liquid crystal layer interposed between the first panel and the second panel,

wherein the first panel includes;

a plurality of gate lines formed on a substrate and including a plurality of oblique portions and a plurality of gate electrodes;

a first insulating layer on the gate line;

a semiconductor layer formed on the first insulating layer;

a plurality of data lines formed at least on the semiconductor layer and intersecting the gate lines to defined trapezoidal pixel areas;

a plurality of drain electrodes separated from the data lines;

a second insulating layer formed at least on portions of the semiconductor layer that are not covered with the data lines and the drain electrodes;

a plurality of pixel electrodes formed on the second insulating layer and connected to the drain electrodes, at least two of the pixel electrodes disposed in each pixel area; and

a plurality of common electrodes formed on the second insulating layer, arranged alternate to the pixel electrodes and connected to the drain electrodes, each common electrode having an edge spaced apart from an edge of the pixel electrodes and substantially parallel to the edge of the pixel electrodes.

9. The liquid crystal display of claim 8, further comprising a sealant disposed around the second panel and confining the liquid crystal layer.

10. The liquid crystal display of claim 9, further comprising a light blocking member located within the sealant and defining a display area for displaying images.

11. The liquid crystal display of claim 10, wherein the light blocking member comprises organic material and is patterned by photolithography.

12. The liquid crystal display of claim 11, further comprising a plurality of spacers including the same layer as the light blocking member.

13. The liquid crystal display of claim 12, wherein the spacers have a height different from the light blocking member.

14. The liquid crystal display of claim 13, wherein the light blocking member has a plurality of depressions.