High frequency chip packages with connecting elements

• US 20040238857A1
• Filed: 12/24/2003
• Published: 12/02/2004
• Est. Priority Date: 08/28/2001
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Beroz, Masud, Kang, Teck-Gyu, Park, Jae M., Kubota, Yoichi, Smith, Lee, Warner, Michael, Urbish, Glenn
• Granted Patent: US 7,176,506 B2
• Time in Patent Office: Days
• US Class Current: 257/232
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/4911 : the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06579 : TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/24 : solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 : characterised by the shape of the housing
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49531 : the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/49861 : Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03H 2009/0019 : Surface acoustic wave multichip
• CPC Class Codes: H03H 9/0542 : consisting of a lateral arrangement H03H9/0566 takes precedence
• CPC Class Codes: H03H 9/0547 : consisting of a vertical arrangement H03H9/0566 takes precedence
• CPC Class Codes: H03H 9/1064 : for surface acoustic wave [SAW] devices
• CPC Class Codes: Y04S 40/20 : Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.

Claims

1. A microelectronic package comprising:

(a) at least one lower chip;

(b) a connecting element extending above said at least one lower chip and extending in at least one horizontal direction beyond said at least one lower chip;

(c) a bottom plane element defining at least a portion of a bottom surface of the package below said at least one lower chip and including a plurality of terminals exposed at said bottom surface and a thermal conductor exposed at said bottom surface, said thermal conductor having area larger than the area of each of said terminals, said thermal conductor being at least partially aligned with said at least one lower chip, at least some of said terminals being electrically connected to at least some of said contacts of said at least one lower chip by said connecting element.

2. A package as claimed in claim 1 wherein said connecting element includes at least one dielectric layer and conductive traces extending along said at least one dielectric layer, at least some of said terminals being connected to at least some of said contacts of said least one lower chip by said traces.

3. A package as claimed in claim 2 further comprising at least one upper chip being disposed above said connecting element.

4. A package as claimed in claim 3 wherein said connecting element has a top surface, a bottom surface, top pads exposed at said top surface and bottom pads exposed at said bottom surface, at least some of said top pads being electrically connected to at least some of said bottom pads, said chips having contacts connected to said pads so that at least some contacts of said at least one lower chip are electrically connected to at least some contacts of said at least one upper chip through said connected top and bottom pads.

5. A package as claimed in claim 3 wherein each said lower chip is an active RF chip and at least one said upper chip includes one or more passive components.

6. A package as claimed in claim 3 wherein each said lower chip has a front face having contacts thereon and a rear face, and wherein the front face of each lower chip faces upwardly, towards said connecting element and the rear face of each lower chip lies in proximity to said thermal conductor.

7. A package as claimed in claim 2 wherein said wherein said terminals include a plurality of active terminals, and wherein said bottom plane element includes a plurality of active leads projecting upwardly from said active terminals to said connecting element.

8. A package as claimed in claim 7 wherein said active leads are formed integrally with said active terminals.

9. A package as claimed in claim 8 wherein said active leads are thicker than said traces.

10. A package as claimed in claim 7 wherein said bottom plane element includes one or more ground busses substantially coplanar with said thermal conductor.

11. A package as claimed in claim 8 further comprising ground leads formed integrally with said ground busses projecting upwardly from said ground busses to said connecting element.

12. A package as claimed in claim 10 wherein said ground buses are spaced laterally from said thermal conductor and said bottom plane element includes ground struts extending between said thermal conductor and said ground busses.

13. A package as claimed in claim 8 wherein said thermal conductor has a plurality of edges, said one or more ground busses extending alongside one or more edges of said thermal conductor, said active contacts being disposed in one or more rows alongside one or more other edges of said thermal conductor.

14. A microelectronic package comprising:

(a) a connecting element including a dielectric element and traces extending along said dielectric element, said connecting element having top and bottom surfaces;

(b) at least one lower chip mounted to said bottom surface of said connecting element, said at least one lower chip having a surface remote from said connecting element defining a lower datum at a level below said connecting element;

(c) a plurality of active terminals disposed at or below said lower datum; and

(d) a plurality of active leads in the form of elongated strips extending between said active terminals and said connecting element, said active leads being connected to at least some of said traces, at least some of said active leads being thicker than said traces.

15. A package as claimed in claim 14 further comprising a mass of encapsulant covering said connecting element and said at least one lower chip, said active leads being embedded in said encapsulant.

16. A package as claimed in claim 15 wherein said mass of encapsulant defines a bottom surface at or below said lower datum, said active terminals being exposed at said bottom surface of the mass.

17. A package as claimed in claim 16 wherein said mass of encapsulant defines edge surfaces extending upwardly from said bottom surface, said active terminals being disposed at said edge surfaces.

18. A package as claimed in claim 14 further comprising at least one upper chip mounted to said top surface of said connecting element.

19. A package as claimed in claim 14 wherein said traces are less than 40 μ

m thick and said active leads are at least 50 μ

m thick.

20. A microelectronic package comprising:

(a) a connecting element including a dielectric element and traces extending along said dielectric element, said connecting element having top and bottom surfaces;

(b) at least one lower chip mounted to said bottom surface of said connecting element, said at least one lower chip having a surface remote from said connecting element defining a lower datum at a level below said connecting element;

(c) a plurality of terminals separate from said connecting element, said terminals being disposed at or below said lower datum; and

(d) a plurality of leads extending between said terminals and said connecting element, said leads being connected to at least some of said traces.

21. A package as claimed in claim 20 further comprising a bottom plane dielectric layer, said terminals being attached to said bottom plane dielectric layer.

22. A package as claimed in claim 20 wherein said connecting element projects horizontally outwardly in at least one direction beyond said at least one lower chip.

23. A package as claimed in claim 22 further comprising at least one upper chip mounted to said top surface of said connecting element.

24. A package as claimed in claim 23 wherein said at least one upper chip is a integrated passive chip including one or more passive components, and wherein said passive chip has horizontal dimensions smaller than the horizontal dimensions of the connecting element.

25. A package as claimed in claim 24 wherein said at least one lower chip is an active RF chip.

26. A package as claimed in claim 20 further comprising a thermal conductor disposed below said lower datum and extending beneath said at least one lower chip.

27. A unitary metallic lead frame comprising:

(a) a plate having top and bottom surfaces and a plurality of edges;

(b) one or more temporary elements;

(c) a plurality of active terminals spaced horizontally from said plate, said active terminals being connected to said plate by said temporary elements;

(d) a plurality of active leads projecting from said active terminals upwardly above the top surface of said plate and horizontally inwardly, toward said plate.

28. A lead frame as claimed in claim 27 wherein said at least a part of each temporary element is disposed horizontally further from said plate that the active terminal or terminals connected to such temporary element.

29. A lead frame as claimed in claim 28 wherein at least some of said active terminals are disposed in rows extending alongside at least some of said edges of said plate and said temporary connecting elements include strips extending beside said rows of active terminals so that each such row is disposed between one said strip and said plate.

30. A lead frame as claimed in claim 29 wherein said edges of said plate include active edges and ground edges, said at least one row of active terminals extending alongside at least one said active edge, the lead frame further comprising at least one ground bus extending alongside at least one said ground edge and spaced horizontally therefrom, and ground struts connecting each said ground bus to said plate.

31. A lead frame as claimed in claim 30 further comprising a plurality of ground leads projecting upwardly from at least one said ground bus and projecting horizontally inwardly toward said plate.

32. A lead frame comprising:

(a) a plurality of terminals;

(b) vertically-extensive active leads projecting upwardly from said terminals;

(c) an inductor; and

(d) temporary elements physically connecting said terminals and said inductor.

33. A lead frame as claimed in claim 32 further comprising inductor leads projecting upwardly from said inductor, said inductor leads and said active leads having upper ends substantially coplanar with one another.

34. A method of making a microelectronic package comprising:

(a) assembling (i) a subassembly incorporating a connecting element with top and bottom surfaces and also incorporating one or more lower chips mounted to said bottom surface with (ii) a bottom plane element including a thermal conductor, said assembling step being performed so that said one or more lower chips overlie said thermal conductor and said connecting element is disposed above said thermal conductor and said one or more lower chips; and

(b) electrically connecting said connecting element to active terminals substantially coplanar with said thermal conductor.

35. A method as claimed in claim 34 wherein said bottom plane element includes active leads projecting upwardly from said active terminals, whereby said connecting element is juxtaposed with said active leads in said assembling step, said electrically connecting step including electrically connecting conductive elements of said connecting element to said active leads.

36. A method as claimed in claim 35 wherein said step of providing said bottom plane element includes providing a unitary lead frame including said active leads, said active terminals and said thermal conductor, the method further comprising the step of disconnecting the active terminals and active leads from said thermal conductor after said assembling step.

37. A method as claimed in claim 36 further comprising the step of encapsulating said active leads, connecting element and chips so as to leave said active terminals and thermal conductor exposed, said disconnecting step including removing temporary elements of said lead frame after said encapsulating step.

38. A method of making a microelectronic package comprising:

(a) assembling

(i) a subassembly incorporating a connecting element with top and bottom surfaces and one or more lower chips mounted to said bottom surface, said one or more lower chips having surfaces remote from said connecting element defining a lower datum and

(ii) a separate bottom plane element including active terminals lying at or below said lower datum; and

(b) electrically connecting said connecting element to said terminals.

39. A method as claimed in claim 38 wherein said bottom plane element has terminal leads projecting upwardly from said terminals, said terminal leads having upper ends, and said connecting element includes a dielectric layer having traces thereon extending to lands exposed at said bottom surface, said assembling step being performed so as to engage said lands with said upper ends of said terminal leads.

40. A method as claimed in claim 38 wherein said bottom plane element includes an inductor, the method further comprising connecting said inductor to said connecting element.

41. A method as claimed in claim 38 wherein said bottom plane element includes a lead frame.

42. A packaged chip comprising:

(a) a bottom package element and a top package element, each said package element having an upwardly facing top surface and a downwardly facing bottom surface, each said package element including one or more dielectric layers and a plurality of conductive elements, said top package element overlying said bottom package element so as to define an interior space between said package elements, said conductive elements of said bottom package element including bottom terminals exposed at the bottom surface of said bottom package element, said conductive elements of said top package element including top terminals exposed at said top surface of said top package element;

(b) one or more chips disposed in said interior space and connected to at least some of said terminals of at least one of said package elements, said conductive elements of said top package element substantially blocking radiative propagation of radio frequency energy between said one or more chips and a space above said top package element.

43. A packaged chip as claimed in claim 42 wherein at least some of said terminals of said top and bottom package elements are electrically connected to one another.

44. A packaged chip as claimed in claim 42 wherein said one or more chips include at least one chip adapted to process radio frequency analog signals.

45. A packaged chip as claimed in claim 42 wherein said one or more chips include at least one radio frequency power amplifier.

46. A packaged chip as claimed in claim 42 wherein said one or more chips includes a first chip and a second chip, each said chip having a front face with contacts thereon, a rear face and edges extending between said front and rear faces, said first and second chips being stacked in face-to-face arrangement with said rear face of said second chip facing toward one of said package elements.

47. A packaged chip as claimed in claim 46 wherein said faces of said second chip are larger than said faces of said first chip, said second chip extending beyond said first chip in at least one horizontal direction.

48. A packaged chip comprising:

(a) at least one chip having at least one edge;

(b) a bottom package element and a top package element, each said package element having an upwardly facing top surface and a downwardly facing bottom surface, said top package element overlying said chip and said bottom package element so that said package elements define an interior space between them and said chip is disposed in said interior space, said conductive elements of said bottom package element including bottom terminals exposed at the bottom surface of said bottom package element, said conductive elements of said top package element including top terminals exposed at said top surface of said top package element, said chip being connected to at least some of said terminals of at least one of said package elements; and

(c) leads extending from one or both of said package elements into or through said interior space, at least some of said conductive elements of said top and bottom package elements being interconnected with one another through said leads.

49. A packaged chip as claimed in claim 48 wherein said conductive elements on at least one of said package elements include traces and at least some of said leads are formed integrally with said traces.

50. A packaged chip as claimed in claim 48 wherein at least some of said leads include wire bonds.

51. A packaged chip as claimed in claim 48 wherein said leads include bottom leads extending between said chip and said bottom package element and top leads extending between said chip and said top package element.

52. A packaged chip as claimed in claim 48 wherein said leads include interconnect leads directly connecting at least some of the conductive elements of one of said package elements to at least some of the conductive elements of another one of said package elements.

53. A packaged chip as claimed in claim 48 further comprising interconnect pillars extending between said top and bottom package elements and interconnecting at least some of the conductive elements on said package elements with one another.

54. A packaged chip as claimed in claim 48 further comprising ball interconnect structures extending between said top and bottom package elements and interconnecting at least some of the conductive elements on said package elements with one another.

55. A packaged chip comprising:

(a) a bottom package element and a top package element, each said package element having an upwardly facing top surface and a downwardly facing bottom surface, said top package element including a plurality of conductive elements, said top chip carrier overlying said bottom chip carrier so as to define an interior space between said chip carriers, said conductive elements of said top package element including top terminals exposed at said top surface of said top package element;

(b) one or more chips disposed in said interior space and connected to at least some of said terminals of at least one of said package elements; and

(c) one or more chips disposed above said top package element and connected to at least some of said terminals of said top package element wherein said conductive elements of said top package element substantially block radiative propagation of radio frequency energy between said one or more chips disposed in said interior space and said one or more chips disposed above said top package element.

56. A packaged chip as claimed in claim 55 wherein said conductive elements of said bottom package element includes bottom terminals exposed at said bottom surface of said bottom package element.

57. A packaged chip as claimed in claim 55 further comprising interconnect pillars extending between said top and bottom package elements and interconnecting at least some of the conductive elements on said package elements with one another.

58. A packaged chip as claimed in claim 55 further comprising leads extending into or through said interior space, at least some of said conductive features of said top and bottom package elements being interconnected with one another through said leads.

59. A packaged chip as claimed in claim 58 wherein said leads include bottom leads extending between said second chip and said bottom package element and top leads extending between said second chip and said top package element.

60. A packaged chip as claimed in claim 55 further comprising a cap panel overlying said top package element and defining a top space between said cap panel and said top package element, said cap panel including conductive elements defining at least a part of an antenna.

61. A packaged chip as claimed in claim 60 wherein said conductive elements of said cap panel define a shield disposed between said antenna and said top space.

62. A packaged chip as claimed in claim 55 wherein said top and bottom package elements and said cap panel include integral portions of a unitary sheet, said unitary sheet having at least two folds therein.

63. An electronic assembly comprising:

(a) a first chip including a radio frequency power amplifier (RFPA);

(b) at least one other chip disposed in vertically stacked relation to said first chip;

(c) a package holding said chips, said package including bottom terminals adapted for mounting to a circuit panel, interconnection between said chips and shielding adapted to substantially block radiative propagation of radio frequency energy between said first chip and said at least one other chip.

64. An electronic assembly as claimed in claim 63 further comprising shielding between said first chip and a space external to said assembly.

65. An electronic assembly as claimed in claim 64 wherein said package further includes at least a portion of an antenna.

66. An electronic assembly as claimed in claim 63 wherein said bottom terminals are adapted for surface mounting to a circuit panel.

67. An electronic assembly as claimed in claim 63 wherein said shielding is adapted to shield said at least one other chip from RF energy radiated from said first chip.

68. A portable electronic communication device including an electronic assembly as claimed in claim 63.

69. A handset including a portable electronic communication device as claimed in claim 68.

70. A cellular mobile communication device including a handset as claimed in claim 69.

71. An electronic assembly comprising:

(a) a first chip including a radio frequency power amplifier (RFPA) adapted to produce at least 10 milliwatts RF power;

(b) a second chip including a surface acoustic wave chip;

(d) a package holding said first and second chips, said package including bottom terminals adapted for mounting to a circuit panel and shielding between said first chip and said second chip.

72. An electronic assembly as claimed in claim 71 further comprising shielding between said first chip and a space external to said assembly.

73. An electronic assembly as claimed in claim 71 wherein said package further includes at least a portion of an antenna.

74. An electronic assembly as claimed in claim 71 wherein said package occupies a volume of less than about 0.5 cm³.

75. An electronic assembly as claimed in claim 71 wherein said shielding is adapted to shield said at least one second chip from RF energy radiated from said first chip.

76. An electronic assembly as claimed in claim 71 wherein said bottom terminals are adapted for surface mounting to a circuit panel.

77. A portable electronic communication device including an electronic assembly as claimed in claim 71.

78. A handset including a portable electronic communication device as claimed in claim 77.

79. A cellular mobile communication device including a handset as claimed in claim 78.

80. A packaged chip comprising:

(a) at least one lower chip; and

(b) a top package element extending above said at least one lower chip and extending in horizontal directions beyond said at least one lower chip, a chip of said at least one lower chip being mounted to said top package element; and

(c) a plurality of leads extending downwardly from said top package element,

wherein said top package element and said leads substantially block radiative propagation of radio frequency energy between said at least one lower chip and a space above said top package element.

81. A packaged chip as claimed in claim 80 wherein said leads form an enclosure extending around edges of said at least one lower chip such that said leads substantially block radiative propagation of radio frequency energy between said at least one lower chip and a space external to said enclosure.

82. A packaged chip as claimed in claim 80 wherein said leads are selected from the group consisting of pre-formed solder features, pillars, wire bonds, and leads formed integrally to a said chip carrier.

83. A packaged chip as claimed in claim 80 wherein at least one of said one or more lower chips includes at least one functional element selected from the group consisting of radio frequency (RF) transmitter, RF power amplifier, RF energy switch, and filter.

84. A packaged chip as claimed in claim 83 wherein said at least one lower chip includes a filter of the surface acoustic wave type.

85. A packaged chip as claimed in claim 84 further comprising one or more upper chips disposed above said package element, said one or more upper chips including at least one functional element selected from the group consisting of RF receiver, low noise amplifier, RF mixer, IF mixer, sampler, oscillator, and signal processor.