Programmable memory device, integrated circuit including the programmable memory device, and method of fabricating same
First Claim
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1. A one-time programmable memory device, comprising:
- an isolation layer for defining an active area of a substrate;
an oxide layer formed on the active area;
a floating gate formed over the active area and the isolation layer;
an inter-gate dielectric layer formed on the floating gate; and
a control gate formed on the inter-gate dielectric layer.
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Abstract
An integrated circuit comprises a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer. The integrated circuit also includes a high and low voltage transistors.
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Citations
23 Claims
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1. A one-time programmable memory device, comprising:
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an isolation layer for defining an active area of a substrate;
an oxide layer formed on the active area;
a floating gate formed over the active area and the isolation layer;
an inter-gate dielectric layer formed on the floating gate; and
a control gate formed on the inter-gate dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 22)
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9. An integrated circuit, comprising:
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a memory device including an isolation layer for defining an active area of a substrate, a tunnel oxide layer formed on the active area, a floating gate formed over the active area and the isolation layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer;
a first transistor including a first gate, a first gate oxide layer interposed between the first gate and the substrate, and a first source region and a first drain region formed in the active area at least one of under and adjacent both sides of the first gate; and
a second transistor including a second gate, a second gate oxide layer interposed between the second gate and the substrate, and a second source region and a second drain region formed in the active area at least one of under and adjacent both sides of the second gate. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit, comprising:
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a plurality of isolation layers for defining a first area, a second area, and a third area in a substrate;
a memory device including a floating gate formed over the first area and at least one isolation layer of the plurality of isolation layers, an inter-gate dielectric layer formed on the floating gate and including a composite layer having a silicon oxide layer and a silicon nitride layer, and a control gate formed on the inter-gate dielectric layer;
a first transistor including a first gate formed of the same material as the control gate, wherein the first gate is formed in the second area of the substrate on a first gate oxide layer having a thickness greater than or equal to a thickness of a tunnel oxide layer formed on the substrate, and a first source region and a first drain region formed in the second area at least one of under and adjacent both sides of the first gate; and
a second transistor including a second gate formed of the same material as the control gate, wherein the second gate is formed in the third area of the substrate on a second gate oxide layer thinner than the first gate oxide layer, and a second source region and a second drain region formed in the third area at least one of under and adjacent both sides of the second gate. - View Dependent Claims (17)
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18. A method of fabricating an integrated circuit, comprising:
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forming a plurality of isolation layers for defining a first active area and a second active area in a substrate;
forming a tunnel oxide layer on the substrate;
forming and patterning a floating gate material on a surface of the substrate including the tunnel oxide layer, to form a floating gate;
forming an inter-gate dielectric layer including a composite layer having a silicon oxide layer and a silicon nitride layer on a surface of the substrate including the floating gate;
etching a portion of the inter-gate dielectric layer in the second active area to form a first gate oxide layer of a high voltage transistor, the first gate oxide layer being thicker than the tunnel oxide layer;
forming and patterning a conductive material on a surface of the substrate including the inter-gate dielectric layer and the first gate oxide layer, to form a control gate and a first gate of the high voltage transistor;
forming an interlayer insulating layer comprising a contact hole on a resultant structure; and
forming a metal interconnection connectable to the control gate via the contact hole. - View Dependent Claims (19, 20, 21, 23)
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Specification