Semiconductor structure having low resistance and method of manufacturing same

• US 20040238876A1
• Filed: 05/29/2003
• Published: 12/02/2004
• Est. Priority Date: 05/29/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Siyoung, Ku, Ja-Hum, Lee, Chang-Won, Kim, Sung-Man, Youn, Sunpil, Heo, Seong-Jun
• Application Number:
  US10/448,534
• Publication Number:
  US 20040238876A1
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming such devices. Between forming a polysilicon layer and a metal layer, an interface reaction preventing layer is created. This reaction preventing layer prevents a buildup of highly resistive materials that would otherwise occur when creating conventional semiconductor devices, as well as having other functions.

Claims

1. A semiconductor device comprising:

a dielectric layer formed on a semiconductor substrate;

a polysilicon layer formed on the dielectric layer;

an interface-reaction preventing layer formed on the polysilicon layer, the interface-reaction preventing layer structured to prevent a reaction between the polysilicon layer and a material layer subsequently formed on the interface-reaction preventing layer;

a barrier layer formed on the interface-reaction preventing layer; and

a metal layer formed on the barrier layer.

2. The semiconductor device as claimed in claim 1 wherein the metal layer comprises tungsten.

3. The semiconductor device as claimed in claim 1 wherein the barrier layer comprises tungsten nitride.

4. The semiconductor device as claimed in claim 1 wherein the interface-reaction preventing layer comprises a metal-silicide.

5. A MOS transistor comprising:

a gate dielectric layer formed on a semiconductor substrate; and

a gate stack formed on the gate dielectric layer, the gate stack having a polysilicon layer disposed on the gate dielectric layer, an interface-reaction preventing layer disposed on the polysilicon layer, a tungsten nitride barrier layer disposed on the interface-reaction preventing layer, and a layer of tungsten disposed on the barrier layer.

6. The MOS transistor of claim 5 wherein the interface-reaction preventing layer comprises tungsten silicide.

7. The MOS transistor of claim 5, further comprising a gate capping layer disposed on the metal layer.

8. A method of manufacturing a semiconductor device, comprising:

forming a dielectric layer on a semiconductor substrate;

forming a polysilicon layer on the dielectric layer;

forming an interface-reaction preventing layer on the polysilicon layer;

forming a metal-nitride barrier layer on the interface-reaction preventing layer; and

forming a metal layer on the metal-nitride barrier layer, wherein forming the metal-nitride barrier layer does not comprise forming a titanium nitride layer.

9. The method of claim 8 wherein forming the metal layer comprises forming a tungsten layer.

10. The method of claim 8 wherein forming the metal-nitride barrier layer comprises forming a tungsten-nitride barrier layer.

11. The method of claim 8 wherein forming the interface-reaction preventing layer comprises forming a metal-silicide layer.

12. The method of claim 11 wherein forming the metal-silicide layer comprises:

depositing a first metal layer on the polysilicon layer; and

heat-treating the first metal layer to cause the first metal layer to react with the polysilicon layer.

13. The method of claim 12 wherein depositing the first metal layer comprises sputtering the first metal layer on the polysilicon layer.

14. The method of claim 12 wherein depositing the first metal layer comprises depositing the first metal layer on the polysilicon layer using chemical vapor deposition.

15. The method of claim 12 wherein depositing the first metal layer comprises depositing the first metal layer on the polysilicon layer using atomic layer deposition.

16. The method of claim 12 wherein heat-treating the first metal layer comprises heat-treating the first metal layer at a temperature of about 850°

C. in ambient nitrogen.

17. The method of claim 11 wherein forming the metal-silicide layer comprises depositing the metal silicide layer on the polysilicon layer.

18. The method of claim 17 wherein depositing the metal silicide layer comprises sputtering the metal silicide layer on the polysilicon layer.

19. The method of claim 17 wherein depositing the metal silicide layer comprises depositing the metal silicide layer on the polysilicon layer using chemical vapor deposition.

20. The method of claim 17 wherein depositing the metal silicide layer comprises depositing the metal silicide layer on the polysilicon layer using atomic layer deposition.

21. The method of claim 8 wherein forming the interface-reaction preventing layer, forming the barrier layer and forming the metal layer are all performed in-situ.

29. The method of claim 18 wherein forming the interface-reaction preventing layer, forming the barrier layer and forming the tungsten layer are performed in-situ.

30. The method of claim 18, further comprising:

patterning the tungsten layer, the barrier layer, the interface-reaction preventing layer and the polysilicon layer to form a gate electrode; and

selectively oxidizing the gate electrode and the semiconductor substrate.

31. The method as claimed in claim 30, further comprising, before the patterning step, forming a gate capping layer on the tungsten layer.

22. A method of manufacturing a MOS transistor, comprising:

forming a gate dielectric layer on a semiconductor substrate;

forming a polysilicon layer on the dielectric layer;

forming an interface-reaction preventing layer on the polysilicon layer;

forming a tungsten-nitride barrier layer on the interface-reaction preventing layer; and

forming a tungsten layer on the barrier layer.

23. The method of claim 22, wherein forming the interface-reaction preventing layer comprises forming a tungsten silicide layer.

24. The method of claim 22, wherein forming the interface-reaction preventing layer comprises:

depositing a first tungsten layer on the polysilicon layer; and

heat-treating the first tungsten layer to cause the first tungsten layer to react with the polysilicon layer to form a tungsten silicide layer.

25. The method of claim 24, wherein depositing the first tungsten layer comprises sputtering the first tungsten layer, depositing the first tungsten layer by chemical vapor deposition, or by depositing the first tungsten layer by atomic layer deposition.

26. The method of claim 24 wherein heat-treating the first tungsten layer comprises heat-treating the first tungsten layer at a temperature of about 850°

C. in ambient nitrogen.

27. The method of claim 22 wherein forming the interface-preventing layer comprises depositing a tungsten silicide layer.

28. The method of claim 27 wherein depositing the tungsten silicide layer comprises sputtering the tungsten silicide layer, depositing the tungsten silicide layer by chemical vapor deposition, or by depositing the tungsten silicide layer by atomic layer deposition.

32. A semiconductor device, comprising:

a substrate having a dielectric layer formed thereon;

a polysilicon layer disposed on the dielectric layer;

a metal layer formed over the polysilicon layer;

a barrier layer formed between the polysilicon layer and the metal layer; and

an additional layer formed between the polysilicon layer and the metal layer, the additional layer distinct from the barrier layer and structured to prevent chemical reactions when the barrier layer is formed.

33. The semiconductor device of claim 32 wherein the additional layer is also structured to prevent oxidants from diffusing to an interface between the barrier layer and the polysilicon layer.

34. The semiconductor device of claim 32 wherein one of the chemical reactions is formation of a relatively high resistance layer.

35. The semiconductor device of claim 32 wherein the additional layer is a tungsten silicide layer formed between the polysilicon layer and the barrier layer.

36. The semiconductor device of claim 35 wherein the barrier layer is a tungsten nitride layer formed on the tungsten silicide layer.

37. The semiconductor device of claim 35 wherein the metal layer is a tungsten layer.

38. The semiconductor device of claim 35, further comprising a silicon nitride layer formed over the tungsten layer.

39. A method for forming a semiconductor device, comprising:

forming a dielectric layer on a semiconductor substrate;

forming a polysilicon layer disposed on the dielectric layer;

forming a tungsten silicide layer on the polysilicon layer;

depositing a tungsten nitride layer on the tungsten silicide layer; and

depositing a tungsten layer on the tungsten nitride layer;

40. The method of claim 39, wherein forming the tungsten silicide layer comprises depositing the tungsten silicide layer.

41. The method of claim 39 wherein forming the tungsten silicide layer comprises:

forming a tungsten layer on the polysilicon layer; and

converting the tungsten layer on the polysilicon layer to the tungsten silicide layer.

42. The method of claim 41 wherein converting the tungsten layer on the polysilicon layer to the tungsten silicide layer comprises heat treating the tungsten layer on the polysilicon layer to form the tungsten silicide layer.

43. The method of claim 42 wherein heat treating comprises heat treating in a nitrogen atmosphere.

44. The method of claim 42 wherein heat treating comprises heat treating in a vacuum.

45. A semiconductor contact structure, comprising:

a polysilicon layer;

a dielectric layer disposed on the polysilicon layer;

a contact hole formed within the dielectric layer;

an interface reaction barrier disposed over the dielectric layer and in the contact hole, the interface reaction barrier adjacent the polysilicon layer within the contact hole;

a second barrier layer disposed on the interface reaction barrier; and

a second metal interconnection layer formed over the second barrier layer.

46. The semiconductor contact structure of claim 45 wherein the interface reaction layer substantially comprises tungsten silicide.

47. A method of forming a contact structure on a semiconductor substrate, comprising;

forming an interlayer dielectric layer having a contact hole therein, the contact hole open to a polysilicon layer formed on the substrate;

forming a interface-reaction preventing layer on the interlayer dielectric layer and within the contact hole, the interface-reaction preventing layer adjacent the polysilicon layer in the contact hole;

forming a barrier layer on the interface-reaction preventing barrier layer; and

forming an interconnection layer adjacent and on the barrier layer.

48. The method of claim 47 wherein forming the interlayer dielectric layer having a contact hole therein comprises:

forming an interlayer dielectric layer on the semiconductor substrate;

creating a contact hole within the interlayer dielectric layer; and

forming a polysilicon layer within the contact hole of the interlayer dielectric layer.

49. The method of claim 47 wherein forming the interlayer dielectric layer having a contact hole therein comprises:

forming the polysilicon layer on the semiconductor substrate;

patterning the polysilicon layer to form a polysilicon line;

forming an interlayer dielectric layer over the substrate and the polysilicon line; and

creating a contact hole within the interlayer dielectric layer at the point of the polysilicon line.