Semiconductor device and method of manufacturing the same

• US 20040238881A1
• Filed: 02/04/2004
• Published: 12/02/2004
• Est. Priority Date: 05/26/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Yoshio
• Granted Patent: US 7,199,425 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film provided on the semiconductor substrate, a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof, a control gate electrode above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, the width of the floating gate electrode changing in the height direction of the non-volatile memory cell in channel width or length direction there, and being thinnest between a region above the bottom surface of the floating gate electrode and a region below the upper surface thereof;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

2. The semiconductor device according to claim 1, wherein the width of the floating gate electrode is the thinnest at an approximately intermediate position between the region above the bottom surface of the floating gate electrode and the region below the upper surface thereof.

3. The semiconductor device according to claim 1, wherein the width of the floating gate electrode gradually increases toward the upper and lower surface of the floating gate electrode from the position where the width of the floating gate electrode is the thinnest.

4. The semiconductor device according to claim 2, wherein the width of the floating gate electrode gradually increases toward the upper and lower surface of the floating gate electrode from the position where the width of the floating gate electrode is the thinnest.

5. The semiconductor device according to claim 3, wherein the width of the floating gate electrode nonlinearly increases.

6. The semiconductor device according to claim 4, wherein the width of the floating gate electrode nonlinearly increases.

7. The semiconductor device according to claim 1, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

8. The semiconductor device according to claim 2, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

9. The semiconductor device according to claim 3, wherein among the upper surface and a side surface of the floating gate electrode, the upper surface thereof is coated with the interelectrode insulating film.

11. The semiconductor device according to claim 1, wherein an area of the tunnel insulating film facing the floating gate electrode is smaller than an area of the interelectrode insulating film facing the floating gate electrode.

12. The semiconductor device according to claim 2, wherein an area of the tunnel insulating film facing the floating gate electrode is smaller than an area of the interelectrode insulating film facing the floating gate electrode.

10. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode, the interelectrode insulating film including a first dielectric region and a second dielectric region having permittivity lower than the first dielectric region, the second dielectric region being provided on a edge of the first dielectric region in the channel length direction of the non-volatile memory cell.

13. A semiconductor device comprising:

a semiconductor substrate; and

a non-volatile memory cell provided on the semiconductor substrate,

the non-volatile memory cell comprising;

a tunnel insulating film provided on the semiconductor substrate;

a floating gate electrode provided on the tunnel insulating film, and including at least one of an empty space region and insulator region;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

14. A method of manufacturing semiconductor device comprising:

a semiconductor substrate;

an isolation region provided on a surface of the semiconductor and including an isolation trench; and

a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising;

a tunnel insulating film;

a floating gate electrode provided on the tunnel insulating film;

a control gate electrode above the floating gate electrode; and

an inter-electrode insulating film provided between the control gate electrode and the floating gate electrode,

the method comprising;

forming an insulating film to be processed into the tunnel insulating film on the semiconductor substrate;

forming a semiconductor film to be processed into the floating gate electrode on the insulating film, the semiconductor film including a side where oxidation rate is the highest between a region above a bottom surface of the semiconductor film and a region below an upper surface thereof;

etching the semiconductor film, the insulating film and the semiconductor substrate, and forming the isolation trench;

oxidizing a surface of the semiconductor film exposed in a process of forming the isolation trench, and forming an oxide film on the surface of the semiconductor film; and

removing the oxide film.

15. The method of manufacturing the semiconductor device according to claim 14, wherein the semiconductor film includes dopant, and the dopant concentration is the highest at the side between a region above a bottom surface of the semiconductor film and a region below an upper surface thereof.

16. A method of manufacturing a semiconductor device comprising:

a semiconductor substrate;

an isolation region provided on a surface of the semiconductor and including an isolation trench; and

a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising;

a tunnel insulating film;

a floating gate electrode provided on the tunnel insulating film;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode,

the method comprising;

forming an insulating film to be processed into the tunnel insulating film and a semiconductor film to be processed into the floating gate electrode on the semiconductor substrate successively;

etching the semiconductor film, the insulating film and the semiconductor substrate, and forming the isolation trench;

forming an isolation film in the isolation trench;

forming a first dielectric region making a part of the interelectrode insulating film and the control gate electrode on a region including the isolation film and the semiconductor film successively; and

forming a second dielectric region having permittivity lower than the first dielectric region and making a part of the interelectrode insulating film in an empty space region formed by etching an exposed surface of the first dielectric region by a predetermined amount in the lateral direction.

17. A method of manufacturing a semiconductor device comprising:

a semiconductor substrate;

an isolation region provided on a surface of the semiconductor and including an isolation trench; and

a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising;

a tunnel insulating film;

a floating gate electrode provided on the tunnel insulating film, and including at least one of an empty space region and insulator region;

a control gate electrode above the floating gate electrode; and

an interelectrode insulating film provided between the control gate electrode and the floating gate electrode,

the method comprising;

forming an insulating film to be processed into the tunnel insulating film, a first semiconductor film making a part of the floating gate electrode, and a polishing stopper film on the semiconductor substrate successively;

etching the polishing stopper film, the first semiconductor film, the insulating film and the semiconductor substrate, forming the isolation trench;

forming an isolation film on a region including the isolation trench and the polishing stopper film so that the isolation trench is filled;

polishing the surface of the isolation trench using the polishing stopper film as a stopper, and removing the isolation film outside the isolation trench;

removing the polishing stopper film; and

forming a second semiconductor film making a part of the floating gate electrode and including an empty space therein on a region including the isolation film and the first semiconductor film to fill a concave portion formed by removing the polishing stopper film.

18. The method of manufacturing the semiconductor device according to claim 17, wherein forming the second semiconductor film is carried out under the condition that the second semiconductor film is deposited on the region conformally.

19. The method of manufacturing the semiconductor device according to claim 17, wherein forming the interelectrode insulating film by thermal oxidation process or low pressure CVD process after the second semiconductor film is formed.

20. The method of manufacturing the semiconductor device according to claim 18, wherein forming the interelectrode insulating film by thermal oxidation process or low pressure CVD process after the second semiconductor film is formed.