High-quality SGOI by oxidation near the alloy melting temperature

• US 20040238885A1
• Filed: 05/30/2003
• Published: 12/02/2004
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bedell, Stephen W., Fogel, Keith E., Domenicucci, Anthony G., Sadana, Devendra K.
• Granted Patent: US 7,049,660 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Claims

1. A method of producing a SiGe-on-insulator substrate material comprising the steps of:

forming a Ge-containing layer on a surface of a first single crystal Si layer, said first single crystal Si layer is present atop a barrier layer that is resistant to Ge diffusion; and

heating said layers to a temperature at or near the melting point of a selected SiGe alloy which causes a substantial reduction in strained relaxation defects while permitting interdiffusion of Ge throughout said first single crystal Si layer and said Ge-containing layer thereby forming a low-defect, substantially relaxed, single crystal SiGe layer atop said barrier layer, said temperature being at or above that which limits generation of stacking fault defects.

2. The method of claim 1 wherein said first single crystal Si layer and said barrier layer are components of a silicon-on-insulator (SOI) substrate.

3. The method of claim 1 wherein said first single crystal Si layer and said barrier layer are components of a non-SOI substrate.

4. The method of claim 1 wherein said barrier layer is a patterned barrier layer.

5. The method of claim 1 wherein said barrier layer is an unpatterned barrier layer.

6. The method of claim 1 wherein said barrier layer comprises crystalline or non-crystalline oxides, or crystalline or non-crystalline nitrides.

7. The method of claim 1 wherein said barrier layer is a buried oxide region.

8. The method of claim 1 wherein said Ge-containing layer is a SiGe alloy or pure Ge.

9. The method of claim 8 wherein said Ge-containing layer is a SiGe alloy comprising up to 99.99 atomic percent Ge.

10. The method of claim 9 wherein said SiGe layer comprises from about 10 to about 35 atomic percent Ge.

11. The method of claim 1 wherein said Ge-containing layer is formed by an epitaxial growth process selected from the group consisting of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and plasma-enhanced chemical vapor deposition.

12. The method of claim 1 further comprising forming a Si cap layer atop said Ge-containing layer prior to heating.

13. The method of claim 12 wherein said Si cap layer comprises epi-Si, a:

Si, single or polycrystalline Si or any combination and multilayer thereof.

14. The method of claim 13 wherein said Si cap layer comprises epi-Si.

15. The method of claim 1 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.

16. The method of claim 12 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.

17. The method of claim 15 wherein said ions comprise hydrogen, deuterium, helium, oxygen, neon, or mixtures and isotopes thereof.

18. The method of claim 16 wherein said ions comprise hydrogen, deuterium, helium, oxygen, neon, or mixtures and isotopes thereof.

19. The method of claim 1 wherein a surface oxide layer forms during said heating step.

20. The method of claim 18 further comprising removing said surface oxide layer utilizing a wet chemical etch process.

21. The method of claim 1 wherein said forming and heating steps are repeated any number of times.

22. The method of claim 1 wherein said heating step is carried out in an oxidizing ambient which comprises at least one oxygen-containing gas.

23. The method of claim 1 wherein said heating step is between the range of 1230 to 1350°

C.

24. The method of claim 22 wherein said at least one oxygen-containing gas comprises O₂, NO, N₂O, ozone, air or mixtures thereof.

25. The method of claim 22 further comprising an inert gas, said inert gas being employed to dilute said at least one oxygen-containing gas.

26. The method of claim 1 wherein said temperature is dependent upon the Ge fraction present in the SiGe layer.

27. The method of claim 1 wherein said substantially relaxed SiGe layer has a thickness of about 2000 nm or less.

28. The method of claim 1 wherein said substantially relaxed SiGe layer has a defect density of about 10⁷ defects/cm² or less.

29. The method of claim 1 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.

30. The method of claim 1 further comprising growing an additional SiGe layer atop said substantially relaxed SiGe layer.

31. The method of claim 30 further comprising forming a strained Si layer atop said additional SiGe layer.

32. The method of claim 1 further comprising forming a strained Si layer atop said substantially relaxed SiGe layer.

33. A substrate material comprising:

a Si-containing substrate;

an insulating region that is resistant to Ge diffusion present atop said Si-containing substrate, said insulating region comprising a crystalline or non-crystalline oxide or a crystalline or non-crystalline nitride; and

a substantially relaxed SiGe layer present atop said insulating region, wherein said substantially relaxed SiGe layer has a thickness of about 2000 nm or less and a defect density of about 10⁷ defects/cm² or less.

34. The substrate material of claim 33 wherein said insulating region is patterned.

35. The substrate material of claim 33 wherein said insulating region is unpatterned.

37. The substrate material of claim 33 wherein said insulating region is a buried oxide region.

38. The substrate material of claim 33 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.

36. (Cancelled)

39. A heterostructure comprising:

a Si-containing substrate;

an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, said insulating region comprising a crystalline or non-crystalline oxide or a crystalline or non-crystalline nitride;

a substantially relaxed SiGe layer present atop the insulating region, wherein the substantially relaxed SiGe layer has a thickness of about 2000 nm or less and a defect density of about 10⁷ defects/cm² or less; and

a strained Si layer formed atop the substantially relaxed SiGe layer.

40. The heterostructure of claim 39 wherein said insulating region is patterned.

41. The heterostructure of claim 39 wherein said insulating region is unpatterned.

43. The heterostructure of claim 39 wherein said insulating region barrier layer is a buried oxide region.

44. The heterostructure of claim 39 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.

45. The heterostructure of claim 39 wherein said strained Si layer comprises an epi-Si layer.

46. The heterostructure of claim 39 wherein alternating layers of relaxed SiGe and strained Si are located atop said strained Si layer.

47. The heterostructure of claim 39 wherein said strained Si layer is replaced with a lattice mismatched compound selected from the group consisting of GaAs and GaP.

42. (Cancelled)