Thin film transistor array panel and a method for manufacturing the same

• US 20040238886A1
• Filed: 12/23/2003
• Published: 12/02/2004
• Est. Priority Date: 01/08/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Bong-Joo, Jeong, Chang-Oh, Cho, Beom-Seok, Lee, Jae-Gab
• Granted Patent: US 7,375,373 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formned on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a first signal line formed on an insulating substrate;

a first insulating layer formed on the first signal line;

a second signal line formed on the first insulating layer and intersecting the first signal line;

a thin film transistor connected to the first and the second signal lines;

a second insulating layer formed on the thin film transistor and having a first contact hole exposing a electrode of the thin film transistor; and

a pixel electrode formed on the second insulating layer and connected to the electrode of the thin film transistor though the first contact hole,

wherein at least one of the first and the second signal lines comprises Ag alloy containing Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr.

2. The thin film transistor array panel of claim 1, wherein oxide of the additive is formed on surfaces of the at least one of the first and the second signal lines comprising Ag alloy.

3. The thin film transistor array panel of claim 2, further comprising red, green and blue color filters formed on respective pixel areas defined by an intersection of the first and the second signal lines, including a photosensitive material containing red, green and blue pigments and being covered by the second insulating layer.

4. A thin film transistor array panel comprising:

a gate wire formed on an insulating substrate and including a gate line, and a gate electrode connected to the gate line;

a gate insulating layer covering the gate wire;

a semiconductor pattern formed on the gate insulating layer;

a data wire including source and drain electrodes formed on the semiconductor pattern, made of the same layer, and separated from each other, and a data line connected to the source electrode and intersecting the gate line to define a pixel area;

a protective layer having a first contact hole exposing the drain electrode; and

a pixel electrode formed on the protective layer and connected to the drain electrode through the first contact hole,

wherein at least one of the gate wire and the data wire comprises Ag alloy containing Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr.

5. The thin film transistor array panel of claim 4, wherein oxide of the additive is formed on surfaces of the at least one of the gate wire and the data wire comprising Ag alloy.

6. The thin film transistor array panel of claim 5, wherein the data wire further comprises a storage capacitor conductor overlapping the gate line or a storage capacitor electrode line to form a storage capacitor, the storage capacitor electrode line including substantially the same layer as the gate line.

7. The thin film transistor array panel of claim 6, wherein the storage capacitor conductor is connected to the drain electrode.

8. The thin film transistor array panel of claim 4, wherein the protective layer comprises an acryl-based organic material or a CVD layer with a dielectric constant equal to or less than 4.0.

9. The thin film transistor array panel of claim 4, wherein the semiconductor pattern has substantially the same shape as the data wire except for a channel area.

10. The thin film transistor array panel of claim 4, further comprising red, green and blue color filters formed on the respective pixel areas, including a photosensitive material containing red, green and blue pigments, and being covered by the protective layer.

11. A thin film transistor array panel comprising:

an insulating substrate;

a gate wire formed on the insulating substrate and including a gate line, a gate electrode and a gate pad;

a gate insulating layer formed on the gate wire and having a contact hole at least exposing the gate pad;

a semiconductor pattern formed on the gate insulating layer;

an ohmic contact pattern formed on the semiconductor pattern;

a data wire formed on the ohmic contact pattern, having substantially the same planar shape as the ohmic contact pattern, and including a source electrode, a drain electrode, a data line, and a data pad;

a protective layer formed on the data wire and a plurality of contact holes exposing the gate pad, the data pad, and the drain electrode; and

a transparent electrode pattern electrically connected to the exposed gate pad, data pad and drain electrode,

wherein at least one of the gate wire and the data wire comprises Ag alloy containing Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr.

12. The thin film transistor array panel of claim 11, wherein oxide of the additive is formed on surfaces of the at least one of the gate wire and the data wire comprising Ag alloy.

13. The thin film transistor array panel of claim 12, further comprising:

a storage capacitor line including substantially the same layer as the gate wire on the substrate;

a storage-capacitor semiconductor overlapping the storage capacitor line and including substantially the same layer as the semiconductor pattern;

a storage-capacitor ohmic contact formed on the storage capacitor semiconductor and having substantially the same planar shape as the storage-capacitor semiconductor; and

a storage capacitor conductor formed on the storage capacitor ohmic contact and having substantially the same planar shape as the storage capacitor semiconductor,

wherein the storage capacitor conductor is partially connected to the transparent electrode pattern.

14. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate wire on an insulating substrate, the gate wire including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line;

forming a gate insulating layer;

forming a semiconductor layer;

depositing a conductive layer and patterning the conductive layer to form a data wire including a data line intersecting the gate line, a data pad connected to the data line, a source electrode connected to the data line and placed close to the gate electrode, and a drain electrode opposite the source electrode with respect to the gate electrode;

forming a protective layer;

patterning the protective layer together with the gate insulating layer to form a plurality of contact holes respectively exposing the gate pad, the data pad and the drain electrode; and

depositing a transparent conductive layer and patterning the conductive layer to form a subsidiary gate pad, a subsidiary data pad and a pixel electrode respectively connected to the gate pad, the data pad, and the pixel electrode,

wherein at least one of the formation of the gate wire and the formation of the data wire comprises;

forming a Ag alloy layer by sputtering Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr;

patterning the Ag alloy layer; and

heat-treating the Ag alloy layer.

15. The method of claim 14, wherein the heat treatment of the Ag alloy layer is performed at 200-400°

C.

16. The method of claim 14, wherein both the data wire and the semiconductor layer are formed by a photolithography step using a photoresist pattern including a first portion, a second portion having a thickness larger than the first portion, and a third portion having a thickness smaller than the first portion.

17. The method of claim 16, wherein in the photolithography step, the first portion is placed between the source and the drain electrodes, and the second portion is placed on the data wire.

18. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate wire on an insulating substrate, the gate wire having a gate line, and a gate electrode connected to the gate line;

forming a gate insulating layer covering the gate wire;

forming a semiconductor pattern on the gate insulating layer;

forming a data wire on the gate insulating layer, the data wire comprising source and drain electrodes including substantially the same layer and separated from each other, and a data line connected to the source electrode;

forming red, green and blue color filters and a first aperture exposing the drain electrode, the color filters including a photosensitive material containing red, green and blue pigments and covering the data wire;

forming a protective layer covering the red, green and blue color filters;

forming a first contact hole exposing the drain electrode; and

forming a pixel electrode connected to the drain electrode through the first contact hole,

wherein at least one of the formation of the gate wire and the formation of the data wire comprises;

forming a Ag alloy layer by sputtering Ag and an additive including at least one selected from the group consisting of Zn, In, Sn and Cr;

patterning the Ag alloy layer; and

heat-treating the Ag alloy layer.

19. The method of claim 18, wherein

the data wire further comprises a storage capacitor conductor overlapping the gate line or a storage capacitor electrode line to form a storage capacitor, the storage capacitor electrode line including substantially the same layer as the gate line;

the red, green and blue color filters having a second aperture exposing the storage capacitor conductor; and

the protective layer has a second contact hole placed within the second aperture and exposing the storage capacitor conductor.

20. The method of claim 18, further comprising:

forming an interlayer insulating layer including silicon nitride or silicon oxide before the formation the color filters.

21. The method of claim 18, wherein the separation of the source and the drain electrodes is made by a photolithography step using a photoresist pattern, and the photoresist pattern has a first portion placed between the source and the drain electrodes and having a first thickness, a second portion having a second thickness larger than the first thickness, and a third portion having a thickness smaller than the first and the second thickness.