Thermally enhanced semiconductor package and fabrication method thereof

• US 20040238945A1
• Filed: 08/05/2003
• Published: 12/02/2004
• Est. Priority Date: 05/28/2003
• Status: Active Grant

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Silicon Precision Industries Company Limited
• Inventors: Huang, Chien-Ping, Hsiao, Cheng-Hsu
• Granted Patent: US 7,019,406 B2
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/92224 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

Claims

1. A thermally enhanced semiconductor package, comprising:

at least one chip having an active surface and an opposite inactive surface, the active surface formed with a plurality of bond pads thereon;

a conductive bump formed on each of the bond pads of the chip;

a heat sink attached to the inactive surface of the chip and having a surface area larger than that of the chip;

an encapsulation body for encapsulating the heat sink, the chip, and the conductive bumps, wherein a plurality of surfaces, other than that for attaching the chip, of the heat sink and ends of the conductive bumps are exposed to outside of the encapsulation body; and

a plurality of first conductive traces formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps.

2. The thermally enhanced semiconductor package of claim 1, further comprising:

a solder mask layer applied over the first conductive traces and formed with a plurality of openings for exposing predetermined portions of the first conductive traces.

3. The thermally enhanced semiconductor package of claim 2, further comprising:

a solder ball formed on each of the exposed portions of the first conductive traces.

4. The thermally enhanced semiconductor package of claim 1, further comprising:

a dielectric layer applied over the first conductive traces and formed with a plurality of vias for exposing predetermined portions of the first conductive traces.

5. The thermally enhanced semiconductor package of claim 4, further comprising:

a plurality of second conductive traces formed on the dielectric layer and electrically connected to the exposed portions of the first conductive traces.

6. The thermally enhanced semiconductor package of claim 5, further comprising:

a solder mask layer applied over the second conductive traces and formed with a plurality of openings for exposing predetermined portions of the second conductive traces.

7. The thermally enhanced semiconductor package of claim 6, further comprising:

a solder ball formed on each of the exposed portions of the second conductive traces.

8. The thermally enhanced semiconductor package of claim 1, wherein the surface for attaching the chip of the heat sink is formed with a plurality of recessed portions to enhance adhesion between the surface of the heat sink and the encapsulation body and adhesion between the surface and the chip.

9. The thermally enhanced semiconductor package of claim 1, wherein the surface for attaching the chip of the heat sink is roughened to enhance adhesion between the surface of the heat sink and the encapsulation body and adhesion between the surface and the chip.

10. The thermally enhanced semiconductor package of claim 1, wherein the conductive bump is selected from the group consisting of solder bump, high lead bump, gold bump, and gold stud bump.

11. A fabrication method of a thermally enhanced semiconductor package, comprising the steps of:

preparing a wafer comprising a plurality of chips each having an active surface and an opposite inactive surface, the active surface formed with a plurality of bond pads thereon;

forming a conductive bump on each of the bond pads of the chips;

singulating the wafer to separate apart the plurality of chips each having a plurality of the conductive bumps formed thereon;

providing a heat sink module plate comprising a plurality of heat sinks, and attaching the chips to a surface of the heat sink module plate, wherein the inactive surface of at least one of the chips is mounted on each of the heat sinks, and the heat sink has a surface area larger than that of the corresponding chip;

fabricating an encapsulation body for encapsulating the heat sink module plate, the chips, and the conductive bumps, and allowing a plurality of surfaces, other than that for attaching the chips, of the heat sink module plate and ends of the conductive bumps to be exposed to outside of the encapsulation body;

forming a plurality of conductive traces on the encapsulation body and electrically connecting the conductive traces to the exposed ends of the conductive bumps;

applying a solder mask layer over the conductive traces and forming a plurality of openings through the solder mask layer for exposing predetermined portions of the conductive traces;

forming a solder ball on each of the exposed portions of the conductive traces; and

cutting the encapsulation body and the heat sink module plate to separate apart the plurality of heat sinks and thereby form a plurality of semiconductor packages each having the individual heat sink.

12. The fabrication method of claim 11, wherein the encapsulation body is partly removed by grinding to expose the ends of the conductive bumps.

13. The fabrication method of claim 11, wherein the conductive bump is selected from the group consisting of solder bump, high lead bump, gold bump, and gold stud bump.

14. The fabrication method of claim 11, wherein the surface for attaching the chips of the heat sink module plate is formed with a plurality of recessed portions to enhance adhesion between the surface of the heat sink module plate and the encapsulation body and adhesion between the surface and the chips.

15. The fabrication method of claim 11, wherein the surface for attaching the chips of the heat sink module plate is roughened to enhance adhesion between the surface of the heat sink module plate and the encapsulation body and adhesion between the surface and the chips.

16. A fabrication method of a thermally enhanced semiconductor package, comprising the steps of:

preparing a wafer comprising a plurality of chips each having an active surface and an opposite inactive surface, the active surface formed with a plurality of bond pads thereon;

forming a conductive bump on each of the bond pads of the chips;

singulating the wafer to separate apart the plurality of chips each having a plurality of the conductive bumps formed thereon;

providing a heat sink module plate comprising a plurality of heat sinks, and attaching the chips to a surface of the heat sink module plate, wherein the inactive surface of at least one of the chips is mounted on each of the heat sinks, and the heat sink has a surface area larger than that of the corresponding chip;

fabricating an encapsulation body for encapsulating the heat sink module plate, the chips, and the conductive bumps, and allowing a plurality of surfaces, other than that for attaching the chips, of the heat sink module plate and ends of the conductive bumps to be exposed to outside of the encapsulation body;

forming a plurality of first conductive traces on the encapsulation body and electrically connecting the first conductive traces to the exposed ends of the conductive bumps;

applying a dielectric layer over the first conductive traces and forming a plurality of vias through the dielectric layer for exposing predetermined portions of the first conductive traces;

forming a plurality of second conductive traces on the dielectric layer and electrically connecting the second conductive traces to the exposed portions of the first conductive traces;

applying a solder mask layer over the second conductive traces and forming a plurality of openings through the solder mask layer for exposing predetermined portions of the second conductive traces;

forming a solder ball on each of the exposed portions of the second conductive traces; and

cutting the encapsulation body and the heat sink module plate to separate apart the plurality of heat sinks and thereby form a plurality of semiconductor packages each having the individual heat sink.

17. The fabrication method of claim 16, wherein the encapsulation body is partly removed by grinding to expose the ends of the conductive bumps.

18. The fabrication method of claim 16, wherein the conductive bump is selected from the group consisting of solder bump, high lead bump, gold bump, and gold stud bump.

19. The fabrication method of claim 16, wherein the surface for attaching the chips of the heat sink module plate is formed with a plurality of recessed portions to enhance adhesion between the surface of the heat sink module plate and the encapsulation body and adhesion between the surface and the chips.

20. The fabrication method of claim 16, wherein the surface for attaching the chips of the heat sink module plate is roughened to enhance adhesion between the surface of the heat sink module plate and the encapsulation body and adhesion between the surface and the chips.