Semiconductor package and method of production thereof

• US 20040238949A1
• Filed: 10/24/2003
• Published: 12/02/2004
• Est. Priority Date: 11/07/2001
• Status: Active Grant

• Current Assignee: Akio Rokugawa, Takahiro Iijima
• Original Assignee: Akio Rokugawa, Takahiro Iijima
• Inventors: Iijima, Takahiro, Rokugawa, Akio
• Granted Patent: US 7,033,934 B2
• Time in Patent Office: Days
• US Class Current: 257/728
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0222 for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09809 Coaxial layout
• CPC Class Codes: H05K 3/4046 using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Abstract

A semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and a connection terminal, that is, a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire at its center, and a method of production of the same.

Claims

1. (Cancelled)

2. (Cancelled)

3. A method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising:

providing an attachment hole passing through a board in a thickness direction and

press-fitting into said attachment hole a capacitor cable comprised of a conductor wire at the core, a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness, and a conductor sheath covering the out circumference of the high dielectric constant material so as to attach the capacitor to said board.

4. A method of production of a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, comprising:

providing an attachment hole passing through a board in a thickness direction,

forming a conductor layer at an inner wall of said attachment hole, and,

press-fitting into said attachment hole formed with said conductor layer a capacitor cable comprised of a conductor wire at the core and a high dielectric constant material coaxially covering the conductor wire at a predetermined thickness so as to attach the capacitor to said board.