Analog open-loop VCO calibration method

• US 20040242175A1
• Filed: 05/27/2003
• Published: 12/02/2004
• Est. Priority Date: 05/27/2003
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lin, Tsung-Hsien
• Granted Patent: US 7,099,643 B2
• Time in Patent Office: Days
• US Class Current: 455/147
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence

Abstract

An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL).

A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

Claims

1. A calibration circuit for a phase locked loop for selecting the frequency of a voltage controlled oscillator (VCO), the calibration circuit comprising:

a frequency divider module coupled to receive a local oscillation signal from the VCO and a reference signal, the frequency divider module producing a divided local oscillation and a divided reference signal, wherein the local oscillation signal and the reference signal are divided by different values to produce a divided oscillation signal substantially equal to the divided reference signal;

a period-to-voltage conversion module coupled to receive the divided local oscillation and the divided reference signal, the period-to-voltage module to convert the divided local oscillation and the divided reference signal to a threshold voltage signal and a reference voltage signal, respectively;

a comparator module coupled to receive the threshold and reference voltage signals, the comparator module for comparing the threshold and reference voltage signals and for producing a frequency adjustment signal; and

a logic module coupled to receive the frequency adjustment signal, the logic module for producing a frequency compensation signal responsive to the frequency adjustment signal.

2. The calibration circuit of claim 1 wherein the frequency adjustment signal comprises a binary signal having at least one of a single bit signal and a multi-bit signal and wherein the binary value of the at least one signal represents an amount of compensation.

3. The calibration circuit of claim 2 wherein the single bit signal defines two logic states and wherein the multi-bit signal defines whether a voltage controlled local oscillation signal frequency should be increased or decreased.

4. The calibration circuit of claim 1 wherein the logic module comprises one of a binary counter and combinational logic, and wherein the logic module produces the frequency compensation signal.

5. The calibration circuit of claim 4 wherein the frequency compensation signal comprises a binary signal having a plurality of values wherein each value of the plurality of values represents a configuration of switched capacitors in a capacitor bank of the VCO.

6. The calibration circuit of claim 1 wherein the frequency divider module comprises a plurality of frequency dividers wherein each of the plurality of frequency dividers divides the received local oscillation signal by a different amount.

7. The calibration circuit of claim 1 wherein the period-to-voltage conversion module comprises a plurality of period-to-voltage converters, one coupled to receive the divided output from each of the frequency dividers.

8. The calibration circuit of claim 7 wherein the period-to-voltage conversion module comprises a charge pump coupled in series with a peak detector.

9. The calibration circuit of claim 8 wherein the charge pump comprises a first current source coupled in series with a pair of complementarily selectable switches, also coupled in series with each other and with a resistive element coupled to circuit common, and wherein the first current source is one of a fixed current value and a programmable current value.

10. The calibration circuit of claim 9 wherein a first capacitor-configured MOSFET is coupled between the pair of complementarily selectable switches and circuit common and wherein the first capacitor-configured MOSFET is one of a fixed capacitance value and a programmable capacitance value.

11. The calibration circuit of claim 10 wherein a first of the selectable switches is coupled to receive a divided oscillating signal and wherein a second of the selectable switches is coupled to receive a complementary divided oscillating signal produced by an inverter that is further coupled to receive the divided oscillating signal.

12. The calibration circuit of claim 7 wherein the peak detector is coupled to receive an output voltage signal from the charge pump and a reset signal wherein the peak detector produces a peak output voltage signal that reflects a peak value of the output voltage signal received from the charge pump so long as the reset signal is not received.

13. The calibration circuit of claim 7 wherein the peak detector comprises an amplifier having a positive input port coupled to receive an output voltage signal from the charge pump, an output port coupled to a gate terminal of a MOSFET, a current source coupled between a drain terminal of the MOSFET and a supply voltage, a capacitor coupled between a source terminal of the MOSFET and circuit common, a negative input port coupled to the MOSFET source terminal, and a selectable reset switch coupled across the capacitor.

14. A method for calibrating a voltage controlled oscillation, comprising:

receiving a local oscillation signal and a reference signal;

dividing the local oscillation signal by “

N1”

to create a first divided local oscillation signal and dividing the local oscillation signal by “

N2”

to create a second divided local oscillation signal, wherein “

N1” and

“

N2”

are not equal;

dividing the reference signal by “

N”

to create a divided reference signal;

converting the first and second divided local oscillation signals to an upper threshold voltage signal and a lower threshold voltage signal, respectively;

converting the divided reference signal to a reference voltage signal;

comparing the reference voltage signal to the upper and lower threshold voltage signals and producing a first and second logic signal therefrom; and

producing a frequency compensation signal based on the first and second logic signals.

15. The method of claim 14 further including dividing the first and second divided local oscillation signals by “

2”

prior to the step of converting to the upper and lower threshold voltage signals, and wherein dividing by “

2”

produces a signal with a 50% duty cycle.

16. The method of claim 14 wherein the step of dividing the reference voltage signal by “

2”

produces a divide reference signal with a 50% duty cycle.

17. The method of claim 14 wherein the frequency compensation signal comprises a multi-state signal for selecting among a plurality of capacitor configurations.

18. A direct conversion Radio Frequency (RF) transceiver integrated circuit comprising:

a baseband processor for producing an outgoing baseband signal and for processing an incoming baseband signal; and

wherein the baseband processor produces a frequency initiation signal for selecting and initiating a local oscillation frequency,

a local oscillator that generates an RF local oscillation signal corresponding to an RF channel, the local oscillator further including a capacitor bank comprising a plurality of switched capacitors, and wherein analog open-loop VCO calibration circuitry selects at least one switched capacitor of the plurality of switched capacitors, the at least one switched capacitor for adjusting the tuning ranged of the VCO;

a receiver section operably coupled to the local oscillator to receive the RF local oscillation signal, wherein the receiver section receives an incoming RF signal, and wherein the receiver section down-converts the incoming RF signal based upon the RF local oscillation signal to produce the incoming baseband signal; and

a transmitter section operably coupled to the local oscillator to receive the RF local oscillation signal, wherein the transmitter section receives an outgoing baseband signal, and wherein the transmitter section up-converts the outgoing baseband signal to produce an outgoing RF signal.

19. The RF transceiver integrated circuit of claim 18, wherein the VCO further comprises:

a voltage variable capacitor (varactor) coupled to receive a control voltage, the varactor for providing a fine VCO frequency control;

an inductor, coupled in parallel to the varactor and the capacitor bank, wherein the parallel coupled inductance and capacitance form a tuned circuit for producing an oscillating current at an RF frequency, and

transconductance circuitry for providing energy to maintain the RF local oscillating signal.

20. The RF transceiver integrated circuit of claim 19, wherein the local oscillator further comprises a phase locked loop (PLL) comprising:

a reference signal;

a frequency divider coupled to receive the RF local oscillating signal and to produce a divided RF local oscillating signal, wherein the frequency divider dividing ratio is set so as to produce a divide RF local oscillating signal approximately equal to the reference signal;

phase frequency detector (PFD) for comparing the divided RF local oscillation signal to the reference signal, the PFD producing frequency correction signals for correcting the frequency of the VCO; and

charge pump circuitry coupled to receive the frequency correction signals and for converting the frequency correction signals into a control voltage, wherein the control voltage causes the VCO frequency to adjust such that frequency correction signals are substantially zero;

21. The RF transceiver integrated circuit of claim 20, wherein the analog open-loop VCO calibration circuitry initiates a calibration cycle upon receipt of the calibration initiation signal received from the coupled baseband processor.

22. The RF transceiver integrated circuit of claim 21, wherein the analog open-loop calibration circuit further comprises:

a frequency divider module coupled to receive a local oscillation signal and a reference signal, the frequency divider module producing a divided local oscillation and a divided reference signal;

a period-to-voltage conversion module coupled to receive the divided local oscillation and the divided reference signal, the period-to-voltage module to convert the divided local oscillation and the divided reference signal to a threshold voltage signal and a reference voltage signal, respectively;

a comparator module coupled to receive the threshold and reference voltage signals, the comparator module for comparing the threshold and reference voltage signals and for producing a frequency adjustment signal; and

a logic module coupled to receive the frequency adjustment signal, the logic module for producing a frequency compensation signal.

23. The calibration circuit of claim 22 wherein the frequency compensation signal comprises a multi-bit signal that defines whether a voltage controlled oscillator signal frequency should be increased or decreased.

24. The calibration circuit of claim 22 wherein the frequency compensation signal comprises a binary signal having a plurality of values wherein each value of the plurality of values represents a configuration of switched capacitors in a capacitor bank of a voltage controlled oscillator.

25. The calibration circuit of claim 22 wherein the logic module comprises combinational logic for producing the frequency compensation signal having more than two logic states responsive to receiving the frequency adjustment signal having more than two logic states.

26. The calibration circuit of claim 22 wherein the frequency divider module comprises a plurality of frequency dividers wherein each of plurality of frequency dividers divides the received local oscillation signal by a different amount.

27. The calibration circuit of claim 22 wherein the period-to-voltage conversion module comprises a plurality of period-to-voltage conversion blocks, one coupled to receive the divided output from each of the frequency dividers.

28. The calibration circuit of claim 27 wherein the period-to-voltage conversion module comprises a charge pump coupled in series with a peak detector.

29. The calibration circuit of claim 28 wherein the charge pump comprises a current source coupled in series with a pair of selectable switches, also coupled in series with each other and with a resistive element.

30. The calibration circuit of claim 27 wherein the selectable switches are complementarily selectable.

31. The calibration circuit of claim 30 wherein a first of the selectable switches is coupled to receive the divided reference signal and wherein a second of the selectable switches is coupled to receive a complementary divided reference signal produced by an inverter that is further coupled to receive the divided reference signal.

32. The calibration circuit of claim 27 wherein the peak detector is coupled to receive an output voltage signal from the charge pump and a reset signal from the logic module, wherein the peak detector produces a peak output voltage signal that reflects a peak value of the output voltage signal received from the charge pump so long as the reset signal is not received.

33. The calibration circuit of claim 27 wherein the peak detector comprises an amplifier having a positive input port coupled to receive an output voltage signal from the charge pump, an output port coupled to a gate terminal of a MOSFET, a current source coupled between a drain terminal of the MOSFET and a supply voltage, a capacitor coupled between a source terminal of the MOSFET and circuit common, a negative input port coupled to the MOSFET source terminal, and a selectable reset switch coupled across the capacitor.

34. A method for open loop calibration of a voltage controlled oscillator (VCO), the method comprising:

receiving, in a calibration circuit logic module, a calibration initiation signal containing at least one frequency divider number;

dividing a local oscillation signal and a reference signal by the at least one frequency divider number to produce a divided local oscillation signal and a divided reference signal;

converting, in a period-to-voltage converter, the divided local oscillation signal into a threshold voltage signal proportional to the period of the divided local oscillation signal;

converting, in a period-to-voltage converter, the divided reference signal into a reference voltage signal proportional to the period of the divided reference signal;

comparing the threshold voltage signal and the reference voltage signal to produce a frequency adjustment signal;

generating a frequency compensation signal from the frequency adjustment signal, said frequency compensation signal comprising a binary signal having a plurality of values; and

setting, with the frequency compensation signal, at least one switched capacitor from a plurality of switched capacitors in a capacitor bank, wherein setting the at least one switched capacitor changes the VCO tuning range.

35. The method of claim 34 wherein the step of dividing the local oscillation signal and the reference signal further includes the step of dividing each signal by two to produce a fifty percent duty cycle signal.

36. The method of claim 34 further includes the step of:

opening a first loop switch in the VCO calibration loop thereby removing a control voltage from the VCO; and

closing a second loop switch in the VCO calibration loop thereby connecting a voltage approximately equal to one-half the supply voltage to the VCO.

37. The method of claim 34 further includes setting a frequency compensation signal to a nominal value and producing a nominal local oscillation signal.

38. The method of claim 37 further including adjusting the frequency compensation signal to approximately match the divided local oscillation signal with the divided reference signal.