Received communication signal processing methods and components for wireless communication equipment

• US 20040242181A1
• Filed: 03/05/2004
• Published: 12/02/2004
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Reznik, Alexander, Hepler, Edward L., Meyer, Jan, Bohnhoff, Peter, Hackett, William C., Ferrante, Steven
• Granted Patent: US 7,433,390 B2
• Time in Patent Office: Days
• US Class Current: 455/323
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7083 Cell search, e.g. using a three-step approach
• CPC Class Codes: H04B 1/7113 Determination of path profile
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 17/364 Delay profiles
• CPC Class Codes: H04B 7/08 at the receiving station
• CPC Class Codes: H04J 13/10 Code generation
• CPC Class Codes: H04L 25/0212 of impulse response

Abstract

A wireless transmit receive unit (WTRU) and methods are used in a wireless communication system to process sampled received signals to establish and/or maintain wireless communications. A selectively controllable coherent accumulation unit produces power delay profiles (PDPs). A selectively controllable post processing unit passes threshold qualified magnitude approximation values and PDP positions to a device such as a rake receiver to determine receive signal paths.

Claims

1. A wireless transmit receive unit (WTRU) for use in a wireless communication system comprising:

an antenna system for receiving wireless signals and producing at least one sequential stream of received signal samples at a selected rate;

a sequential array of N vector correlators VC[1] to VC[N], each configured for coherently accumulating L sized sets of sequential received signal samples;

said vector correlators coupled with said antenna system such that for any given series of N+L-1 samples, S₁ to SN+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1], each vector correlator VC[i], where i=1 to N, processes respective samples S_i to S_i+L-1;

a sequence generator configured to selectively generate known sequences sought to be detected in received wireless signals and coupled with said vector correlators such that as each vector correlator VC[i], where i=1 to N, processes a set of L sequential samples within a series of samples S₁ to S_N+L-1, a generated element Gj of a given known sequence of L generated elements, G₀ to G_L-1, is mixed with sample Si+j in VC[i] to produce a mixed value that is coherently accumulated in VC[i]; and

vector correlator accumulator control circuitry configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs an accumulated value after accumulating a selected multiple M of sets of L accumulated mixed values whereby power delay profiles (PDPs) of a series of at least N elements E₁ to E_N are produced where each PDP element E_i represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N.

2. The invention of claim 1 wherein said vector correlator accumulator control circuitry is configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs a selected number P of accumulated values whereby power delay profiles (PDPs) of a series of N*P elements E₁ to E_N*P are produced where each PDP element E_i+(j*N) represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N and j=0 to P-1.

3. The invention of claim 1 wherein:

said antenna system is configured with multiple antennas to produce multiple sequential streams of received signal samples at the selected rate, and

said vector correlators each include a controllable antenna switch device configured to select a sample stream from among the multiple sample streams from which to receive samples for processing by the respective vector correlator.

4. The invention of claim 3 wherein vector correlator array includes antenna switch control circuitry configured to control said antenna switch devices such that for any given series of N+L-1 samples, S₁ to S_N+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1] received from a particular sample stream, the respective antenna switch device of each vector correlator VC[i], where i=1 to N, is controlled to select the particular sample stream for the vector correlator VC[i] to process respective samples S_i to S_i+L-1 received therefrom.

5. The invention of claim 1 wherein:

said vector correlators are each configured with a plurality of n accumulator devices AD₁ to AD_n;

each respective accumulator device AD_j, for j=1 to n, is selectively coupled to said sequence generator to receive elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values whereby the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different sequences.

6. The invention of claim 1 wherein:

said sequence generator includes a scrambling code generator and n signature code generators and is configured with n outputs SGO₁ to SGO_N such that each sequence generator output SGO_j outputs a different signature/scrambling code combination sequence of generated elements;

said vector correlators are each configured with a plurality of n accumulator devices AD₁ to AD_n;

each respective accumulator device AD_j, for j=1 to n, is selectively coupled to said sequence generator to receive elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values whereby the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different sequences.

7. The invention of claim 1 wherein the vector correlator array operates at a speed that is 48 times faster than the selected sampling rate.

8. The invention of claim 1 further comprising:

an interpolator coupled with said vector correlators and configured to produce expanded PDPs by increasing the number of elements from P to a desired multiple of P through interpolation; and

a post processing unit for processing the expanded PDPs that includes;

a magnitude approximation device configured to provide magnitude approximation values of expanded PDP values; and

a threshold evaluation device;

said post processing device configured to pass magnitude approximation values and associated PDP position values that are qualified by the threshold device to a RAKE receiver type of device.

9. The invention of claim 8 wherein the WTRU is configured for use as a Node B in a Universal Mobile Telecommunications System (UMTS)

10. The invention of claim 8 wherein the WTRU is configured for use as a Uesr Equipment (UE) in a Universal Mobile Telecommunications System (UMTS).

11. A method for processing received wireless signals comprising:

producing at least one sequential stream of received signal samples at a selected rate;

coherently accumulating L sized sets of sequential received signal samples using a sequential array of N vector correlators VC[1] to VC[N] such that for any given series of N+L-1 samples, S₁ to S_N+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1], each vector correlator VC[i], where i=1 to N, processes respective samples S_i to S_i+L-1;

selectively generating known sequences sought to be detected in received wireless signals;

mixing the generated known sequences during said coherent accumulation such that as each vector correlator VC[i], where i=1 to N, processes a set of L sequential samples within a series of samples S₁ to S_N+L-1, a generated element Gj of a given known sequence of L generated elements, G₀ to G_L-1, is mixed with sample Si+j in VC[i] to produce a mixed value that is coherently accumulated in VC[i]; and

selectively controlling an accumulated mixed value output of each vector correlator such that each vector correlator outputs an accumulated value after accumulating a selected multiple M of sets of L accumulated mixed values whereby power delay profiles (PDPs) of a series of at least N elements E₁ to E_N are produced where each PDP element E_i represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N.

12. The method of claim 11 wherein the vector correlators are selectively controlled such that each vector correlator outputs a selected number P of accumulated values whereby power delay profiles (PDPs) of a series of N*P elements E₁ to E_N*P are produced where each PDP element E_i+(j*N) represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N and j=0 to P-1.

13. The method of claim 11 wherein multiple sequential streams of received signal samples at the selected rate are produced, and

a sample stream from among the multiple sample streams is selected from which to receive samples for processing by each respective vector correlator.

14. The method of claim 13 wherein said sample steam selection is controlled that for any given series of N+L-1 samples, S₁ to S_N+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1] received from a particular sample stream, each vector correlator VC[i], where i=1 to N, is controlled to select the particular sample stream for the vector correlator VC[i] to process respective samples S_i to S_i+L-1 received therefrom.

15. The method of claim 11 where the vector correlators are each configured with a plurality of n accumulator devices AD₁ to AD_n wherein during said coherent accumulation, each respective accumulator device AD_j, for j=1 to n, selectively receives elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values whereby said coherent accumulation can concurrently produce n PDPs, each corresponding to one of the n different sequences.

16. The method of claim 15 wherein:

said sequence generating is performed using a scrambling code generator and n signature code generators configured to output in parallel n sequences SGO₁ to SGO_N such that each sequence SGO_j is a different signature/scrambling code combination of generated elements; and

during said coherent accumulation, each respective accumulator device AD_j, for j=1 to n, selectively receives elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample is processed with n different sequences to produce n accumulations of mixed values where by n PDPs are concurrently produced, each corresponding to one of the n different sequences.

17. The method of claim 11 wherein said coherent accumulation is performed at a speed that is 48 times faster than the selected sampling rate.

18. The method of claim 11 further comprising:

producing expanded PDPs by increasing the number of elements from P to a desired multiple of P through interpolation; and

processing the expanded PDPs, including producing magnitude approximation values of expanded PDP values, such that magnitude approximation values and associated PDP position values that are qualified by the threshold device are passed to a RAKE receiver type of device.

19. A coherently accumulation unit for processing sequential streams of received signal samples in a wireless transmit receive unit (WTRU) used in a wireless communication system comprising:

a sequential array of N vector correlators VC[1] to VC[N], each configured for coherently accumulating L sized sets of sequential received signal samples;

said vector correlators configured to process streams of received signal samples such that for any given series of N+L-1 samples, S₁ to S_N+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1], each vector correlator VC[i], where i=1 to N, processes respective samples S_i to S_i+L-1;

a sequence generator configured to selectively generate known sequences sought to be detected in received wireless signals and coupled with said vector correlators such that as each vector correlator VC[i], where i=1 to N, processes a set of L sequential samples within a series of samples S₁ to S_N+L-1, a generated element Gj of a given known sequence of L generated elements, G₀ to G_L-1, is mixed with sample Si+j in VC[i] to produce a mixed value that is coherently accumulated in VC[i]; and

vector correlator accumulator control circuitry configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs an accumulated value after accumulating a selected multiple M of sets of L accumulated mixed values whereby power delay profiles (PDPs) of a series of at least N elements E₁ to E_N are produced where each PDP element E_i represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N.

20. The invention of claim 19 wherein said vector correlator accumulator control circuitry is configured to selectively control an accumulated mixed value output of each vector correlator such that each vector correlator outputs a selected number P of accumulated values whereby power delay profiles (PDPs) of a series of N*P elements E₁ to E_N*P are produced where each PDP element E_i+(j*N) represents the coherent accumulation of M*L mixed values produced by the vector correlator VC[i], where i=1 to N and j=0 to P-1.

21. The invention of claim 19 wherein said vector correlators each include a controllable switch device configured to select a sample stream from among multiple sample streams from which to receive samples for processing by the respective vector correlator and further comprising switch control circuitry configured to control said switch devices such that for any given series of N+L-1 samples, S₁ to S_N+L-1, where the sample S₁ is to be a first element of a set processed by the first vector correlator VC[1] received from a particular sample stream, the respective antenna switch device of each vector correlator VC[i], where i=1 to N, is controlled to select the particular sample stream for the vector correlator VC[i] to process respective samples S_i to S_i+L-1 received therefrom.

22. The invention of claim 19 wherein:

said vector correlators are each configured with a plurality of n accumulator devices AD₁ to AD_n;

each respective accumulator device AD_j, for j=1 to n, is selectively coupled to said sequence generator to receive elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values whereby the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different sequences.

23. The invention of claim 19 wherein:

said sequence generator includes a scrambling code generator and n signature code generators and is configured with n outputs SGO₁ to SGO_n such that each sequence generator output SGO_j outputs a different signature/scrambling code combination sequence of generated elements;

said vector correlators are each configured with a plurality of n accumulator devices AD₁ to AD_n;

each respective accumulator device AD_j, for j=1 to n, is selectively coupled to said sequence generator to receive elements of a common generated sequence for mixing with signal samples processed by the respective vector correlator such that each sample can be processed with n different sequences to produce n accumulations of mixed values where by the vector correlator array can concurrently produce n PDPs, each corresponding to one of the n different sequences.

24. A wireless transmit receive unit (WTRU) for use in a wireless communication system that receives wireless signals from other WTRUs such that the relative timing of each wireless signal as received by the WTRU is known and the wireless signals are defined by series of a predetermined number J of symbols, SYM(0) to SYM(J-1), transmitted in timeslots of system time frames where each symbol has a predetermined bit length B, the WTRU comprising:

a power delay profile (PDP) production unit configured to produces PDPs that each have a selected number L of sequential elements that have values representing coherent accumulation of sequential sets of a selected number p received samples mixed with a known sequence, where p equals B times for a selected positive integer I, p=B*I; and

said power delay profile production unit configured to selectively produce successive PDPs with respect to received WTRU wireless signals such that when N wireless signals are concurrently received, PDPs are produced for respective wireless signals in order of earliest to latest received signal, WS(0) to WS(N-1), derived from the known timing, starting with a first earliest received wireless signal WS(0) beginning on the occurrence a symbol SYM(j) with respect to time slot having the receive timing of the first wireless signal WS(0) and continuing successively for each subsequently received wireless signal WS(n), for n=1 to N-1, beginning, after a time alignment delay based on the known timing of the wireless signal WS(n), on the occurrence a symbol SYM((j+(I*n))mod J) with respect to a time slot having the receive timing of the wireless signal WS(n) whereby the processing of the PDP for the latest received wireless signal WS(N-1) begins with a cumulative delay of D chips relative to the start of the symbol SYM((j+(I*(N-1)))mod J) with respect to a time slot having the receive timing of the first wireless signal so that the next PDP produced for the first received wireless signal begins on the occurrence the symbol SYM(K) with respect to a time slot having the receive timing of the first wireless signal WS(0), where K is the greatest integer less than ((j+(I*(N-1))+(D/B)) mod J.

25. The invention of claim 24 wherein the power delay profile (PDP) production unit is configured to produces PDPs that have values representing coherent accumulation of sequential sets of received samples representing J symbols so that p=J*B whereby said power delay profile production unit selectively produces successive PDPs with respect to received WTRU wireless signals such that when N wireless signals are concurrently received, PDPs are produced for respective wireless signals in order of earliest to latest received signal, WS(0) to WS(N-1), derived from the known timing, starting with a first earliest received wireless signal WS(0) beginning on the occurrence a symbol SYM(j) with respect to time slot having the receive timing of the first wireless signal WS(0) and continuing successively for each subsequently received wireless signal WS(n), for n=1 to N-1, beginning, after a time alignment delay based on the known timing of the wireless signal WS(n), on the occurrence a symbol SYM(j) with respect to a time slot having the receive timing of the wireless signal WS(n) whereby the processing of the PDP for the latest received wireless signal WS(N-1) begins with a cumulative delay of D chips relative to the start of the symbol SYM(j) with respect to a time slot having the receive timing of the first wireless signal so that the next PDP produced for the first received wireless signal begins on the occurrence the symbol SYM(K) with respect to a time slot having the receive timing of the first wireless signal WS(0), where K is the greatest integer less than (j+(D/B)) mod J.

26. The invention of claim 25 where the WTRU is configured for use in a Universal Mobile Telecommunications System (UMTS) having system time slot of 2560 chips wherein the power delay profile (PDP) production unit is configured to produces PDPs for wireless signals received on a pilot channel formatted 10 symbols of 256 bits per pilot channel time slot.

27. The invention of claim 24 further comprising:

an interpolator coupled with said power delay profile (PDP) production unit and configured to produce expanded PDPs by increasing the number of elements from P to a desired multiple of P through interpolation; and

a post processing unit for processing the expanded PDPs that includes;

a magnitude approximation device configured to provide magnitude approximation values of expanded PDP values; and

a threshold evaluation device;

said post processing device configured to pass magnitude approximation values and associated PDP position values that are qualified by the threshold device to a RAKE receiver type of device.

28. The invention of claim 27 wherein the WTRU is configured for use as a Node B in a Universal Mobile Telecommunications System (UMTS)

29. The invention of claim 27 wherein the WTRU is configured for use as a Uesr Equipment (UE) in a Universal Mobile Telecommunications System (UMTS).

30. A method for controlling power delay profile (PDP) production in a wireless transmit receive unit (WTRU) that receives wireless signals from other WTRUs such that the relative timing of each wireless signal as received by the WTRU is known and the wireless signals are defined by series of a predetermined number J of symbols, SYM(0) to SYM(J-1), transmitted in timeslots of system time frames where each symbol has a predetermined bit length B, where the PDPs each have a selected number L of sequential elements that have values representing coherent accumulation of sequential sets of a selected number p received samples mixed with a known sequence, where p equals B times for a selected positive integer I, p=B*I, the method comprising:

selectively producing successive PDPs with respect to received WTRU wireless signals such that when N wireless signals are concurrently received, PDPs are produced for respective wireless signals in order of earliest to latest received signal, WS(0) to WS(N-1), derived from the known timing, starting with a first earliest received wireless signal WS(0) beginning on the occurrence a symbol SYM(j) with respect to time slot having the receive timing of the first wireless signal WS(0) and continuing successively for each subsequently received wireless signal WS(n), for n=1 to N-1, beginning, after a time alignment delay based on the known timing of the wireless signal WS(n), on the occurrence a symbol SYM(j+(I*n))mod J) with respect to a time slot having the receive timing of the wireless signal WS(n) whereby the processing of the PDP for the latest received wireless signal WS(N-1) begins with a cumulative delay of D chips relative to the start of the symbol SYM(j+(I*(N-1)))mod J) with respect to a time slot having the receive timing of the first wireless signal so that the next PDP produced for the first received wireless signal begins on the occurrence the symbol SYM(K) with respect to a time slot having the receive timing of the first wireless signal WS(0), where K is the greatest integer less than ((j+(I*(N-1))+(D/B)) mod J.

31. The method of claim 30 where the PDPs have values representing coherent accumulation of sequential sets of received samples representing J symbols so that p=J*B, wherein successive PDPs with respect to received WTRU wireless signals are selectively produced such that when N wireless signals are concurrently received, PDPs are produced for respective wireless signals in order of earliest to latest received signal, WS(0) to WS(N-1), derived from the known timing, starting with a first earliest received wireless signal WS(0) beginning on the occurrence a symbol SYM(j) with respect to time slot having the receive timing of the first wireless signal WS(0) and continuing successively for each subsequently received wireless signal WS(n), for n=1 to N-1, beginning, after a time alignment delay based on the known timing of the wireless signal WS(n), on the occurrence a symbol SYM(j) with respect to a time slot having the receive timing of the wireless signal WS(n) whereby the processing of the PDP for the latest received wireless signal WS(N-1) begins with a cumulative delay of D chips relative to the start of the symbol SYM(j) with respect to a time slot having the receive timing of the first wireless signal so that the next PDP produced for the first received wireless signal begins on the occurrence the symbol SYM(K) with respect to a time slot having the receive timing of the first wireless signal WS(0), where K is the greatest integer less than (j+(D/B)) mod J.

32. The method of claim 31 where the method is implemented in a Universal Mobile Telecommunications System (UMTS) having system time slot of 2560 chips wherein PDPs are selectively produced for wireless signals received on a pilot channel formatted 10 symbols of 256 bits per pilot channel time slot.

33. The method of claim 30 further comprising:

producing expanded PDPs by increasing the number of elements from P to a desired multiple of P through interpolation; and

processing the expanded PDPs, including producing magnitude approximation values of expanded PDP values, such that magnitude approximation values and associated PDP position values that are qualified by the threshold device are passed to a RAKE receiver type of device.