DRAM memory page operation method and its structure

• US 20040243879A1
• Filed: 06/12/2004
• Published: 12/02/2004
• Est. Priority Date: 01/16/2001
• Status: Abandoned Application

• Current Assignee: Chien-Zu Hou, Hsiu-Ying Hsu
• Original Assignee: Chien-Zu Hou, Hsiu-Ying Hsu
• Inventors: Hou, Chien-Zu, Hsu, Hsiu-Ying
• Application Number:
  US10/867,063
• Publication Number:
  US 20040243879A1
• Time in Patent Office: Days
• US Class Current: 714/8
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

The present invention relates to a DRAM memory page operation method and its structure. The disclosed method comprises a set up procedure and an operation procedure. The set up procedure tests and finds out whether any deficit exists in the memory page of the memory and establishes a table of look-aside buffer that indicates defective locations and the corresponding new locations. The real operation procedure is executed after the set up procedure completes. It establishes a fast page lookup table according to results in the set up procedure for instructing the memory page or memory unit to operate in the normal access mode or the page operation mode. Good memory pages then replace bad memory pages according to the records in the fast page lookup table and the bad memory pages are moved to addresses at the very end of the memory so that the memory can operate even with deficits. Thus, no deficit in a single DRAM memory page/unit will halt the whole system.

Claims

1. A DRAM memory page operation method, which comprises a set up procedure and an operation procedure;

wherein said set up procedure includes the following steps;

a) testing memory to find out whether any deficit exists in a memory page;

b) fault page reallocation to establish a table of look-aside buffer (TLB) so as to indicate defective locations and the corresponding new locations mapped into;

c) page attribute processing to establish selection items that define memory page operation modes in the TLB;

d) establishing a fast page lookup table (FPLT) according to the result of the set up procedure for indicating whether the memory page or memory unit is operating under the normal access mode or the page operation mode; and

wherein

said operation procedure then checks the FPLT and said TLB so as to replacing bad memory pages by good ones and appending said bad ones to the latest addresses in the memory.

2. A DRAM memory page operation method as recited in claim 1, wherein:

said step of testing memory is started by the basic input/output system (BIOS).

3. A DRAM memory page operation method as recited in claim 1, wherein:

said page attributes include such selection items as read only, write only, write once and read once that are applicable to both defective memory and normal memory.

4. A DRAM memory page operation method as recited in claim 1, wherein:

after memory page replacing in said operation procedure the set up procedure will report the number of total memory pages, excluding bad memory pages, to the computer system so that no access to defective memory pages will occur when the next time the memory pages are accessed.

5. A DRAM memory page operation method as recited in claim 1, wherein:

said operation procedure further comprises unique two-level mapping procedures for checking the mapping bits in the FPLT stored in SRAM so as to determine memory pages.

6. A DRAM memory page operation method as recited in claim 5, wherein:

the first mapping indicates that a memory page is operating in the normal access mode when the bit is “

0”

.

7. A DRAM memory page operation method as recited in claim 5, wherein:

the second mapping indicates that the memory page is operating in the page operation mode when the bit is “

1” and

the system checks the TLB stored in flash memory in the controller to confirm the page attributes and the actual mapping addresses.

8. A DRAM system structure, which comprises:

a) at least one Dynamic Random Access Memory (DRAM) including a plurality of memory pages (cells);

b) a memory controller including;

i) a controller, which controls the access of each memory page and has memory for storing the set up procedure result described in claim 1;

ii) an SRAM, which stores a FPLT that has a plurality of indication bits mapping into memory pages for indicating whether the memory pages are operating under the normal access mode or the page operation mode.

9. The DRAM structure as recited in claim 8, wherein:

said memory is a flash memory or a volatile memory of RAM.

10. The DRAM structure as recited in claim 8, wherein:

the size of said SRAM corresponds to the number of memory pages.