Multi-level boot hierarchy for software development on an integrated circuit

• US 20040243978A1
• Filed: 01/12/2004
• Published: 12/02/2004
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Simon Robert Walmsley
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Granted Patent: US 7,783,886 B2
• Time in Patent Office: Days
• US Class Current: 717/120
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

A method of enabling software development for an integrated circuit, the integrated circuit being configured to run a boot program that prevents unverified software from subsequently being loaded onto, or run by, the integrated circuit, the method including the step of loading an intermediate program onto the integrated circuit, the intermediate program being customised for a particular one or more of a plurality of potential integrated circuits that, when run on the processor, enables loading or running of code on only the particular one or more integrated circuits.

Claims

1. A method of enabling software development for an integrated circuit, the integrated circuit being configured to run a boot program that prevents unverified software from subsequently being loaded onto, or run by, the integrated circuit, the method including the step of loading an intermediate program onto the integrated circuit, the intermediate program being customised for a particular one or more of a plurality of potential integrated circuits that, when run on the processor, enables loading or running of code on only the particular one or more integrated circuits.

2. A method according to claim 1, wherein the intermediate program enables the loading or running of unverified code on only the particular one or more integrated circuits.

3. A method according claim 2, wherein the intermediate program enables the loading or running of the code only when the code includes data indicative of the particular one or more integrated circuits.

4. A method according claim 1, wherein the intermediate program includes an intermediate boot key, such that the intermediate program enables loading or running of the code only when the code is verified in accordance with the intermediate boot key.

5. An integrated circuit configured to run a boot program that prevents unverified software from subsequently being loaded onto, or run by, the integrated circuit.

6. An integrated circuit according to claim 5, programmed with program code configured to:

receive software data and a digital signature of the software data

generate a first digest from the software data; and

compare the first digest against a second digest obtained via the digital signature that accompanied the received software data;

wherein the program is considered valid when the first and second digests match.

7. An integrated circuit according to claim 6, wherein one or both of the digests were generated using a SHA1 function.

8. An integrated circuit according to claim 6, wherein the boot program contains a plurality of keys, and one of the keys is selected for use in generating the first digest, the key being selected in accordance with a selection criterion.

9. An integrated circuit according to claim 8, wherein the selection criterion is time-based, a particular one of the keys being selected depending on the time the selection is made.

10. An integrated circuit according to claim 8, wherein the selection criteria relates to a physical arrangement or configuration of the integrated circuit.

11. An integrated circuit according to claim 10, wherein the physical arrangement or configuration includes one or more of the following:

one or more pads wired to a reference voltage or to ground;

one or more fuses, one or more of which has been blown;

or

the contents of non-volatile memory.

12. An integrated circuit according to claim 5, programmed with program code configured to:

receive encrypted software data,

decrypt the software data; and

validate the software data;

wherein the decrypted software is executed only when the validation is successful.

13. An integrated circuit according to claim 12, wherein the encryption function is RSA.

14. An integrated circuit according to claim 12, wherein the boot program contains a plurality of keys, and one of the keys is selected for use in decrypting the software data, the key being selected in accordance with a selection criterion.

15. An integrated circuit according to claim 14, wherein the selection criterion is time-based, a particular one of the keys being selected depending on the time the selection is made.

16. An integrated circuit according to claim 14, wherein the selection criteria relates to a physical arrangement or configuration of the integrated circuit.

17. An integrated circuit according to claim 16, wherein the physical arrangement or configuration includes one or more of the following:

one or more pads wired to a reference voltage or to ground;

one or more fuses, one or more of which has been blown;

or

the contents of non-volatile memory.