Method of fabricating vertical structure compound semiconductor devices

• US 20040245543A1
• Filed: 06/03/2004
• Published: 12/09/2004
• Est. Priority Date: 06/04/2003
• Status: Active Grant

• Current Assignee: Verticle, Inc.
• Original Assignee: Myung C. Yoo
• Inventors: Yoo, Myung Cheol
• Granted Patent: US 7,384,807 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: Y10S 438/956 Making multiple wavelength emissive device

Abstract

A method of fabricating a vertical structure opto-electronic device includes fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate, and then removing the substrate using a laser lift-off process. The method then fabricates a metal support structure in place of the substrate. In one aspect, the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating. In one aspect, the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes copper. Advantages of the invention include fabricating vertical structure LEDs suitable for mass production with high reliability and high yield.

Claims

1. A method of fabricating a vertical structure opto-electronic device, comprising the step of:

fabricating a plurality of vertical structure opto-electronic devices on a crystal substrate;

removing the substrate using a laser lift-off process; and

fabricating a metal support structure in place of the substrate.

2. The method of claim 1, wherein the step of fabricating a metal support structure in place of the substrate includes the step of plating the metal support structure using at least one of electroplating and electro-less plating.

3. The method of claim 1, wherein the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes Cu.

4. The method of claim 2, wherein the vertical structure is a GaN-based vertical structure, the crystal substrate includes sapphire and the metal support structure includes Cu.

5. The method of claim 1, further comprising the step of:

fabricating a buffer layer between the opto-electronic devices and the metal support structure.

6. The method of claim 2, further comprising the step of:

fabricating a buffer layer between the opto-electronic devices and the metal support structure.

7. The method of claim 1, wherein the step of fabricating a metal support structure is performed on either a p-type metal contact or n-type metal contact surface.

8. The method of claim 2, wherein the step of fabricating a metal support structure is performed on either a p-type metal contact or n-type metal contact surface.

9. The method of claim 1, wherein the step of fabricating a metal support structure in place of the substrate includes the step of:

depositing an ITO (Indium Tin Oxide) layer forming an n-contact;

depositing an Au buffer layer over the ITO layer; and

plating a Cu layer over the Au layer using at least one of electroplating and electro-less plating.

10. The method of claim 3, wherein the GaN-based vertical structure includes a buffer layer comprising an AlGaN buffer layer in addition to a GaN or AlN buffer layer to provide the thermal diffusion barrier to protect polymer-base adhesive layer.

11. The method of claim 10, wherein trenches are formed from the GaN layer through the substrate according to the following rules:

a) trench dimension is substantially similar to the laser beam spot size, for example 7×

7 mm to relieve shock wave during laser lift-off process;

b) the trenches are beneficially narrower than about 100 microns wide and extend no deeper than about 3 microns into the sapphire substrate; and

c) the trenches are beneficially formed using reactive ion etching, preferably inductively coupled plasma reactive ion etching (ICP RIE).

12. The method of claim 10, wherein in order to relieve shock wave and easy de-lamination during a de-bonding process after laser lift-off, double coating for adhesion bonding layer using polymer-base adhesives, such as super glue and SU-8 5 epoxy between GaN epi layer and the support wafer according to the following steps:

a) super glue layer is applied using spin coating;

b) the super glue layer thickness is approximately 30 micron-thick;

c) the SU-8 5 is also applied using spin coating with thickness thicker than 20 micron.

d) SU-8 5 is cured with UV lamp; and

e) the UV lamp transparent sapphire support is used for curing SU-8 5 epoxy.

13. The method of claim 3, further comprising the step of using a diffuser plate made of materials transparent to a laser beam by disposing the diffuser plate between a laser beam and the sapphire substrate in order to obtain uniform laser beam power distribution.

14. The method of claim 3, further comprising the step of performing ICP RIE etching and polishing on the lifted GaN wafer, wherein the etching and polishing exposes and produces an atomically flat surface of pure n-GaN, and wherein the flat surface is particularly beneficial in producing high reflectivity from a reflective structure to be subsequently deposited.

15. The method of claim 3, further comprising the step of depositing a transparent conductive reflective layer using electron beam evaporation on the bottom of the structure, wherein ITO (Indium Tin Oxide) is preferably used for the n-contact is reflector.

16. The method of claim 3, further comprising the step of depositing a soft Cu alloy layer in order to gradually soften stress build up due to a thick metal layer, wherein the initial soft Cu alloy layer thickness is set up to ˜

10 μ

m, and wherein the plating rate is set up to 3˜

5 μ

m/hour.

17. The method of claim 16, further comprising the step of depositing a hard Cu layer in order to provide structural stiffness, wherein a plating rate of hard Cu plating is up to 20 μ

m/hour, wherein for the Cu alloy plating, metal alloy plating solutions containing tin (Sn) and iron (Fe) are mixed with a Cu sulfate solution to improve the mechanical strength and the electrical conductivity of the Cu alloy support layer, wherein the total thickness of Cu alloy support layer is 70˜

90 μ

m, and wherein at the end of the Cu alloy plating, 0.5˜

1 μ

m-thick Au layer is electroplated to protect Cu alloy layers from oxidation.

18. The method of claim 3, further comprising the step of dicing individual devices by chemical or laser scribing.

19. A vertical structure electro-optic device manufactured according to the method of claim 1.

20. A vertical structure electro-optic device manufactured according to the method of claim 2.

21. A vertical structure electro-optic device manufactured according to the method of claim 3.

22. A vertical structure opto-electronic device, comprising a plurality of layers including:

a GaN-based light emitting diode and at one contact in proximity to the top thereof;

an ITO (Indium Tin Oxide) contact layer disposed below the fabricating a vertical structure laser diode on a crystal substrate;

an buffer layer including Au adjacent the ITO layer; and

a support layer including copper adjacent the Au layer.

23. The vertical structure opto-electronic device of claim 22 wherein the support layer is constructed using at least one of electroplating and electro-less plating.