[CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME]

• US 20040245580A1
• Filed: 07/23/2004
• Published: 12/09/2004
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megit Acquisition Corp.
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 8,421,158 B2
• Time in Patent Office: Days
• US Class Current: 257/379
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

The present invention provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.

Claims

1. A process for forming a chip structure with a resistor, comprising:

providing a semiconductor substrate;

forming a plurality of electronic devices and a resistor in a surface layer of the semiconductor substrate;

forming a plurality of dielectric layers and a plurality of circuit layers over the semiconductor substrate, the dielectric layers stacked over the semiconductor substrate, the dielectric layers having a plurality of via holes, each of the circuit layers disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

forming a passivation layer over the dielectric layers and the circuit layers; and

forming a circuit line over the passivation layer, wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

2. The process as claimed in claim 1, wherein the resistor is formed by doping boron, phosphorous, arsenic or gallium into the semiconductor substrate through the surface of the semiconductor.

3. The process as claimed in claim 1, wherein the resistor is made of a material of constituting a N well, a P well, a N⁺ diffusion region or a P⁺ diffusion region.

4. The process as claimed in claim 1, further comprising forming an insulation layer over the passivation layer and the insulation layer covering the circuit line.

5. The process as claimed in claim 4, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

6. The process as claimed in claim 1, further comprising forming an insulation layer between the passivation layer and the circuit line.

7. The process as claimed in claim 6, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

8. A process for forming a chip structure with a resistor, comprising:

providing a semiconductor substrate;

forming a plurality of electronic devices in a surface layer of the semiconductor substrate;

forming a plurality of dielectric layers, a plurality of circuit layers and a resistor over the semiconductor substrate, the dielectric layers stacked over the semiconductor substrate, the dielectric layers having a plurality of via holes, the resistor disposed on one of the dielectric layers, each of the circuit layers disposed on corresponding one of the dielectric layers respectively,

wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

forming a passivation layer over the dielectric layers and the circuit layers; and

forming a circuit line over the passivation layer, wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

9. The process as claimed in claim 8, wherein the resistor is formed by depositing polysilicon using a chemical-vapor-deposition (CVD) process.

10. The process as claimed in claim 8, wherein the resistor is formed by depositing polysilicon using a chemical-vapor-deposition (CVD) process and then doping boron, phosphorous, arsenic or gallium into the deposited polysilicon.

11. The process as claimed in claim 8, wherein the resistor is formed by depositing aluminum, copper, tungsten, an aluminum alloy or a cooper alloy using a vapor-deposition process.

12. The process as claimed in claim 8, further comprising forming an insulation layer over the passivation layer, the insulation layer covering the circuit line.

13. The process as claimed in claim 12, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

14. The process as claimed in claim 8, further comprising forming an insulation layer between the passivation layer and the circuit line.

15. The process as claimed in claim 14, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

16. A process for forming a chip structure with a resistor, comprising:

providing a semiconductor substrate;

forming a plurality of electronic devices in a surface layer of the semiconductor substrate;

forming a plurality of dielectric layers and a plurality of circuit layers over the semiconductor substrate, the dielectric layers stacked over the semiconductor substrate,

the dielectric layers having a plurality of via holes, each of the circuit layers disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

forming a passivation layer over the dielectric layers and the circuit layers;

forming a resistor over the passivation layer by a depositing process; and

forming a circuit line over the passivation layer, wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

17. The process as claimed in claim 16, wherein the resistor is formed by depositing aluminum, an aluminum alloy, copper, a copper alloy, a nickel-chromium alloy, a nickel-tin alloy, tantalum nitride, tantalum or tungsten using a vapor-deposition method or an electroplating method.

18. The process as claimed in claim 16, further comprising forming an insulation layer over the passivation layer, the insulation layer covering the circuit line.

19. The process as claimed in claim 18, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

20. The process as claimed in claim 16, further comprising forming an insulation layer between the passivation layer and the circuit line.

21. The process as claimed in claim 20, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

22. A chip structure with a resistor, comprising:

a semiconductor substrate having a surface layer;

a plurality of electronic devices positioned in the surface layer of the semiconductor substrate;

a resistor positioned in the surface layer of the semiconductor substrate;

a plurality of dielectric layers stacked over the semiconductor substrate and the dielectric layers having a plurality of via holes;

a plurality of circuit layers each disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

a passivation layer positioned over the dielectric layers and the circuit layers; and

a circuit line positioned over the passivation layer, wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

23. The chip structure as claimed in claim 22, wherein a material constituting the resistor is silicon with a dopant selected from the group of boron, phosphorous, arsenic and gallium.

24. The chip structure as claimed in claim 22, wherein the resistor is made of a material of constituting a N well, a P well, a N⁺ diffusion region or a P⁺ diffusion region.

25. The chip structure as claimed in claim 22, further comprising an insulation layer positioned over the passivation layer and the insulation layer covering the circuit line.

26. The chip structure as claimed in claim 25, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

27. The chip structure as claimed in claim 22, further comprising an insulation layer positioned between the passivation layer and the circuit line.

28. The chip structure as claimed in claim 27, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

29. A chip structure with a resistor, comprising:

a semiconductor substrate;

a plurality of electronic devices positioned in a surface layer of the semiconductor substrate;

a plurality of dielectric layers stacked over the semiconductor substrate and the dielectric layers having a plurality of via holes;

a plurality of circuit layers each disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

a resistor positioned on one of the dielectric layers;

a passivation layer positioned over the dielectric layers and the circuit layers; and

a circuit line positioned over the passivation layer,

wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

30. The chip structure as claimed in claim 29, wherein a material of constituting the resistor is polysilicon.

31. The chip structure as claimed in claim 29, wherein a material of constituting the resistor is polysilicon with a dopant selected from the group of boron, phosphorous, arsenic and gallium.

32. The chip structure as claimed in claim 29, wherein a material constituting the resistor is aluminum, copper, tungsten, an aluminum alloy or a copper alloy.

33. The chip structure as claimed in claim 29, further comprising an insulation layer positioned over the passivation layer and the insulation layer covering the circuit line.

34. The chip structure as claimed in claim 33, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

35. The chip structure as claimed in claim 29, further comprising an insulation layer positioned between the passivation layer and the circuit line.

36. The chip structure as claimed in claim 35, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

37. A chip structure with a resistor, comprising:

a semiconductor substrate;

a plurality of electronic devices positioned in a surface layer of the semiconductor substrate;

a plurality of dielectric layers stacked over the semiconductor substrate and the dielectric layers having a plurality of via holes;

a plurality of circuit layers each disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices;

a passivation layer positioned over the dielectric layers and the circuit layers; and

a resistor formed by a depositing process and positioned over the passivation layer; and

a circuit line positioned over the passivation layer,

wherein the circuit line passes through the passivation layer to electrically connect the resistor to the circuit layers.

38. The chip structure as claimed in claim 37, wherein a material constituting the resistor is aluminum, an aluminum alloy, copper, a copper alloy, a nickel-chromium alloy, a nickel-tin alloy, tantalum nitride, tantalum or tungsten.

39. The chip structure as claimed in claim 37, further comprising an insulation layer positioned over the passivation layer and the insulation layer covering the circuit line.

40. The chip structure as claimed in claim 39, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.

41. The chip structure as claimed in claim 37, further comprising an insulation layer positioned between the passivation layer and the circuit line.

42. The chip structure as claimed in claim 41, wherein the material of constituting the insulation layer is made of polyimide (PI), benzocyclobutene (BCB), porous dielectric material, parylene, elastomer or low k dielectric material.