Image display device with increased margin for writing image signal

• US 20040246246A1
• Filed: 04/15/2004
• Published: 12/09/2004
• Est. Priority Date: 06/09/2003
• Status: Abandoned Application

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tobita, Youichi
• Application Number:
  US10/824,515
• Publication Number:
  US 20040246246A1
• Time in Patent Office: Days
• US Class Current: 345/205
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/325 the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

Pixels are arranged in rows and columns and gate lines are arranged corresponding to the rows of pixels in a display panel. Deactivation transition detect circuit detects transition of a selected gate line from a selected state to a non-selected state in the gate lines. An operation related to data writing in the next cycle is started in accordance with a deactivation transition detect signal detecting the transition. In an active matrix type display device, a write margin for data writing of the next cycle is increased when a selected gate line transits to a non-selected state.

Claims

1. An image display device, comprising:

a plurality of pixel elements arranged in rows and columns;

a plurality of gate lines, arranged corresponding to the rows of pixel elements and driven to a selected state in a prescribed sequence, each for transmitting, when selected, a select signal for driving pixel elements of a corresponding row to a selected state;

non-select transition detect circuitry arranged for said plurality of gate lines for detecting transition of a gate line in a selected state to a non-selected state; and

internal circuitry for performing an operation related to next image data writing in response to said non-select transition detect circuitry detecting the transition to the non-selected state.

2. The image display device according to claim 1, wherein

said internal circuitry includes a gate line select circuit for driving the select signal for a next gate line in said prescribed sequence to an active state in response to a signal indicating detection of the transition to the non-selected state from said non-select transition detect circuitry.

3. The image display device according to claim 1, wherein

said internal circuitry includes;

a shift circuit for generating a basic select signal driving said plurality of gate lines to a selected state in said prescribed sequence in synchronization with a clock signal,

a plurality of gate line activation prohibiting circuits, arranged corresponding to the respective gate lines, each being set to a first state in accordance with activation of a select signal for a corresponding gate line and set to a second state in accordance with activation of a non-selection transition detecting signal from said non-select transition detect circuitry, and

gate line drive circuits, arranged corresponding to the gate lines, for driving the select signal to a corresponding gate line in accordance with a corresponding basic select signal and the second state of the gate line activation prohibiting circuit of a preceding stage in said prescribed sequence.

4. The image display device according to claim 3, wherein

said internal circuitry further includes a plurality of initialization transistors, arranged corresponding to the respective gate lines, each for setting said non-selection transition detecting signal to an inactive state in response to a corresponding gate line being driven to the selected state.

5. The image display device according to claim 1, wherein

said non-select transition detect circuitry includes a plurality of deactivation detect circuits arranged corresponding to the respective gate lines,

the inactivation detect circuits each include;

a capacitive element having one electrode coupled to a corresponding gate line,

a precharge element for precharging other electrode of said capacitive element to a prescribed potential, and

a detection transistor for activating a non-select transition detecting signal indicating the transition in response to at least a potential of the other electrode of said capacitive element.

6. The image display device according to claim 5, wherein

the inactivation detect circuits each further includes a control transistor enabling activation of said non-select transition detect signal by said detect transistor in response to an inactive state of an adjacent gate line in said prescribed sequence.

7. The image display device according to claim 1, wherein

said plurality of pixel elements each include a display pixel element performing a displaying operation in accordance with an applied image signal.

8. The image display device according to claim 1, wherein

said plurality of pixel elements includes a plurality of normal display pixel elements displaying an image and a dummy pixel element arranged in alignment with the normal display pixel elements,

said plurality of gate lines include a normal gate line connecting to the normal display pixel elements, and a plurality of dummy gate lines connecting to the dummy pixel element, and

said non-select transition detect circuitry detects transition to the non-selected state according to a potential of the dummy gate lines to activate a non-select transition detect signal indicating the transition.

9. The image display device according to claim 8, wherein

said internal circuitry drives a designated normal gate line to the selected state in accordance with activation of said non-select transition detect signal.

10. The image display device according to claim 8, further comprising:

dummy select circuitry for generating a dummy basic gate signal sequentially selecting said plurality of dummy gate lines in accordance with a clock signal;

a plurality of activation prohibiting circuits, arranged corresponding to the respective dummy gate lines, each being set to a first state in accordance with activation of a select signal for a corresponding dummy gate line and set to a second state in accordance with activation of said non-select transition detect signal; and

a plurality of dummy gate drive circuits, arranged corresponding to the respective dummy gate lines, each for driving a corresponding dummy gate line to the selected state in accordance with the second state of an activation prohibiting circuit of a preceding stage in a dummy gate line selection sequence and a dummy basic select signal for a corresponding dummy gate line.

11. The image display device according to claim 1, wherein

said internal circuitry includes;

a latch circuit for latching and outputting digital pixel data for next image data in accordance with activation of a non-select transition detecting signal indicating the transition, and

a multiplexer for converting the data outputted from said latch circuit into an analog signal for outputting the converted analog signal.

12. The image display device according to claim 11, further comprising:

a plurality of data lines arranged corresponding to the respective columns of the pixel elements; and

data line drive circuitry driving the data lines in accordance with the signal received from said multiplexer.

13. The image display device according to claim 1, wherein

the pixel elements each include a display element having a counter electrode arranged opposing to a data storage node, and

said internal circuitry includes a voltage generate circuit for alternately selecting first and second voltages to be applied to said counter electrode in response to activation of said non-select transition detecting signal indicating the transition, a polarity of the voltage of said counter electrode changing for each activation of said non-select transition detect signal.