Novel multi-state memory
First Claim
1. A multi-state memory comprising:
- a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors;
one or more tracking cells for each of said multi-states, associated with each of said plurality of sectors;
read circuitry for reading raw data associated with the programmed state of said tracking cells;
converter circuitry for converting said raw data to digital form; and
a memory controller for establishing desired read points for each of a plurality of physical states, based upon said raw data converted to digital form read from each said tracking cell.
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Abstract
Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.
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Citations
41 Claims
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1. A multi-state memory comprising:
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a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors;
one or more tracking cells for each of said multi-states, associated with each of said plurality of sectors;
read circuitry for reading raw data associated with the programmed state of said tracking cells;
converter circuitry for converting said raw data to digital form; and
a memory controller for establishing desired read points for each of a plurality of physical states, based upon said raw data converted to digital form read from each said tracking cell. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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2. A multi-state memory comprising:
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a plurality of EEPROM memory cells, each for storing one of a plurality of multi-states, organized into a plurality of sectors, each sector comprising an array of rows and columns;
cell operating circuitry comprising;
sense circuitry organized in a column oriented manner;
steering elements organized in a column oriented manner; and
select circuitry organized in a row oriented manner, wherein one or more selected cells along a row are capable of being read simultaneously;
a reference source;
verification circuitry for selected cells for applying to associated steering elements of said selected cells conditions corresponding to verification of corresponding write state and for receiving read data using said reference source for determining if a selected one of said memory cells has been adequately programmed to the conduction characteristics associated with a desired programmed state; and
write circuitry organized in a column oriented manner, wherein a selected one or more of said memory cells are capable of being written simultaneously with associated steering elements set to corresponding write states, and including termination circuitry for terminating the programming of selected memory cells along said row being programmed when said verification circuitry indicates said selected memory cells have been adequately programmed to then-desired states. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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27. A memory cell comprising:
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a read/write path;
a read only path; and
a floating gate common to said read/write and said read only paths. - View Dependent Claims (28)
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29. A memory comprising:
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a plurality of EEPROM memory cells organized into a plurality of sectors, each sector including at least one wear detecting cell comprising;
a read/write path;
a read only path; and
a floating gate common to said read/write and said read only paths; and
control circuitry for detecting the difference in conduction characteristics of said read/write and read only paths during reading, to measure the amount of wear of said wear detecting cell. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A method of operating a memory which comprises a plurality of word lines, and a plurality of EEPROM memory cells, each cell uniquely associated with one word line and one bit line, each memory cell having a floating gate electrode, a steering electrode, and an erase electrode, said method comprising the steps of:
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selecting one or more of said memory cells along a row;
controlling the magnitude of a steering voltage applied to said steering electrodes of said selected one or more memory cells, on a cell by cell basis;
establishing erase potentials on said selected one or more memory cells, thereby removing charge from said floating gates of said selected one or more memory cells, wherein the magnitude of electron removal from each floating gate is established on a cell by cell basis by the magnitude of the steering potential applied to its associated steering electrode. - View Dependent Claims (36, 37, 38, 39, 40, 41)
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Specification