DEVICE FOR WLAN BASEBAND PROCESSING WITH DC OFFSET REDUCTION

• US 20040247046A1
• Filed: 06/09/2003
• Published: 12/09/2004
• Est. Priority Date: 06/09/2003
• Status: Active Grant

• Current Assignee: Ali SPA (Bessemer Group Incorporated)
• Original Assignee: Ali SPA (Bessemer Group Incorporated)
• Inventors: Hsiao, Yung-Sheng
• Granted Patent: US 7,215,722 B2
• Time in Patent Office: Days
• US Class Current: 375/319
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.

Claims

1. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising:

a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal;

an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal;

a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at a first output a gain control signal and at a second output a gain state signal, the gain control signal instructing the previous system to adjust a strength of the intermediate analogue signal;

a DC estimator coupled to the output of the ADC for estimating the DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset;

a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input the first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal;

an arithmetic module coupled to the output of the DAC and to the output of the programmable filter bank, the arithmetic module subtracting the feedback signal from the filtered signal for canceling DC offsets of the programmable filter bank and the ADC; and

a DCF (DC-Filter) controller coupled to the second output of the DC estimator and to the second output of the gain controller for receiving the second DC offset signal to instruct the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system, wherein the DCF controller receives the gain state signal and generates the filter state signal at an output, to which the filter state input of the programmable filter bank is coupled.

2. The baseband processor of claim 1 wherein one of the plurality of the frequency pass characteristics of the programmable filter bank is a notch filter characteristic.

3. The baseband processor of claim 1 wherein one of the plurality of the frequency pass characteristics of the programmable filter bank is a high pass filter characteristic.

4. The baseband processor of claim 1 wherein the programmable filter bank comprises a plurality of filters.

5. The baseband processor of claim 4 wherein the plurality of filters being coupled to the previous system, the programmable filter bank further comprises a multiplexer for receiving output signals of the plurality of filters and generating at the output of the programmable filter bank the filtered signal.

6. The baseband processor of claim 1 wherein the DC estimator further comprises:

an accumulator coupled to the output of the ADC for averaging the digital signal received from the ADC and generating at an output an average signal according to an accumulating control signal received from an accumulating control input;

a shifter coupled to the output of the accumulator for shifting the average signal to the DAC according to a shifting control signal received from a shifting control input and generating at the first output of the DC estimator the first DC offset signal; and

a control unit for generating at a first output the accumulating control signal and at a second output the shifting control signal, the accumulating control input of the accumulator being coupled to the first output of the control unit and the shifting control input of the shifter being coupled to the second output of the control unit.

7. The baseband processor of claim 1 further comprising a demodulator coupled to the output of the ADC for demodulating the digital signal.

8. The baseband processor of claim 7 wherein the gain controller further comprises a receiver state input coupled to an output of the demodulator for receiving a receiver state signal.

9. The baseband processor of claim 8 wherein the gain controller further comprises:

a gain estimator coupled to the output of the ADC for estimating the strength of the digital signal received from the ADC and generating at an output a strength information signal;

a GCSM (Gain Control State Machine) coupled to the output of the gain estimator and to the output of the demodulator through the receiver state input for generating at an RXG (Receiver Gain) output an RXG signal and for generating at the second output of the gain controller the gain state signal according to the strength information signal received from the gain estimator and the receiver state signal received from the demodulator; and

an RXGDAC (Receiver Gain DAC) coupled to the RXG output of the GCSM for converting the RXG signal received from the GCSM into an analogue form and generating at the first output of the gain controller the gain control signal.

10. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising:

a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal;

an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal;

a DC estimator coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at a first output a first DC offset signal corresponding to the DC offset; and

a DCF (DC-Filter) controller comprising a first input coupled to the first output of the DC estimator for receiving the first DC offset signal and generating a filter state signal at an output coupled to the filter state input for instructing the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system.

11. The baseband processor of claim 10 wherein the programmable filter bank comprises a plurality of filters coupled to the previous system, the programmable filter bank further comprises a multiplexer for receiving output signals of the plurality of filters and generating at the output of the programmable filter bank the filtered signal.

12. The baseband processor of claim 11 further comprising:

a DAC (Digital-to-Analogue Converter) coupled to a second output of the DC estimator for receiving as an input a second DC offset signal and generating at an output a feedback signal corresponding to the second DC offset signal; and

an arithmetic module coupled between the output of the programmable filter bank and the input of the ADC and having an input coupled to the output of the DAC for receiving the feedback signal, the arithmetic module subtracting the feedback signal from the filtered signal for canceling DC offsets of the programmable filter bank and the ADC.

13. The baseband processor of claim 11 wherein the DC estimator further comprises:

an accumulator coupled to the output of the ADC for averaging the digital signal received from the ADC and generating at an output an average signal according to an accumulating control signal received from an accumulating control input;

a shifter coupled to the output of the accumulator for shifting the average signal to the DCF controller according to a shifting control signal received from a shifting control input and generating the first DC offset signal and the second DC offset signal; and

a control unit for generating at a first output the accumulating control signal and at a second output the shifting control signal, the accumulating control input of the accumulator being coupled to the first output of the control unit and the shifting control input of the shifter being coupled to the second output of the control unit.

14. The baseband processor of claim 10 further comprising a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at an output a gain control signal, the gain control signal instructing the previous system to adjust the strength of the intermediate analogue signal.

15. The baseband processor of claim 10 further comprising a demodulator coupled to the output of the ADC for demodulating the digital signal.

16. The baseband processor of claim 15 further comprising a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at an output a gain control signal, the gain control signal instructing the previous system to adjust a strength of the intermediate analogue signal, the gain controller further comprising a receiver state input coupled to an output of the demodulator for receiving a receiver state signal.

17. An electronic device for processing an analogue signal received from a previous system, the electronic device comprising:

a signal conversion loop for receiving the analogue signal and converting the analogue signal into a digital signal;

a digital demodulator for receiving and demodulating the digital signal; and

a DC (direct current) offset reduction circuit coupled between the signal conversion loop and the digital demodulator and comprising a first DC reduction section for reducing a DC offset of the digital signal and a second DC reduction section for reducing a DC offset stemming from the previous system.

18. The electronic device of claim 17 wherein the signal conversion loop comprises:

a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal; and

an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal.

19. The electronic device of claim 18 wherein the first DC reduction section comprises:

a DC estimator coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset;

a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input a first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal; and

an arithmetic module coupled between the output of the programmable filter bank and the input of the ADC for receiving the feedback signal, the arithmetic module subtracting the feedback signal from the filtered signal for canceling the DC offset of the digital signal.

20. The electronic device of claim 19 wherein the second DC reduction section comprises:

a DCF (DC-Filter) controller comprising a first input coupled to the second output of the DC estimator for receiving the second DC offset signal and generating a filter state signal at an output coupled to the filter state input for instructing the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system; and

a gain controller coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at an output a gain control signal, the gain control signal instructing the previous system to adjust a strength of the analogue signal, the gain controller further comprising a receiver state input coupled to an output of the demodulator for receiving a receiver state signal.