FLOATING-GATE MEMORY CELL HAVING TRENCH STRUCTURE WITH BALLASTIC-CHARGE INJECTOR AND ARRAY OF MEMORY CELLS

• US 20040248371A1
• Filed: 06/06/2003
• Published: 12/09/2004
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Chih-Hsin Wang
• Inventors: Wang, Chih-Hsin
• Granted Patent: US 6,958,513 B2
• Time in Patent Office: Days
• US Class Current: 438/330
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.

Claims

1. An electrically erasable and programmable read only memory device comprising:

a bulk material;

a first layer of semiconductor material over said bulk material and having a first conductivity type;

a first region formed in between said bulk material and said first layer, and having a second conductivity type;

a trench formed into a surface of said first layer and having a sidewall and a bottom;

a second region formed in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type;

a channel region in said first layer between said first region and said second region, and extending generally along said sidewall of said trench;

an electrically conductive floating gate disposed adjacent to and insulated from said channel region;

an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate; and

an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.

2. The device of claim 1, wherein said bulk material includes a semiconductor material having the first conductivity type.

3. The device of claim 1, wherein said bulk material includes an insulator.

4. The device of claim 1, wherein at least a portion of said floating gate is disposed laterally adjacent to said channel region.

5. The device of claim 1, wherein a portion of said floating gate is disposed adjacent to and insulated from a portion of said first region.

6. The device of claim 1, wherein:

said sidewall of said trench is generally perpendicular to a surface of said first layer; and

said bottom of said trench is generally parallel to said surface of said first layer

7. The device of claim 1, wherein said trench extends through said second region, said first layer with said bottom formed within said first region.

8. The device of claim 1, wherein said trench extends through said second region, said first layer and said first region with said bottom formed within said bulk material.

9. The device of claim 1, wherein said floating gate includes:

a first portion disposed laterally adjacent to and insulated from said sidewall of said trench; and

a second portion disposed over and insulated from said bottom of said trench.

10. The device of claim 1;

wherein said floating gate includes;

a first portion disposed over and insulated from at least a portion of said second region;

a second portion disposed laterally adjacent to and insulated from said sidewall of said trench; and

a third portion disposed over and insulated from said bottom of said trench.

11. The device of claim 1, further comprising a first insulating layer having a first portion disposed over said second region and a surface of said first layer, and a second portion disposed over said bottom and laterally adjacent to said sidewall of said trench.

12. The device of claim 1, wherein:

said control gate and said tunneling gate overlap with each other at an overlapping region; and

at least a portion of said floating gate is disposed under the overlapping region.

13. The device of claim 9, wherein said floating gate has a generally rectangular shaped structure.

14. The device of claim 9, wherein said floating gate has a generally “

V”

shaped structure.

15. The device of claim 10, wherein said floating gate has a generally “

T”

shaped structure.

16. The device of claim 1, wherein said control gate includes:

a first portion disposed generally over and insulated from at least a portion of said second region and a surface of said first layer; and

a second portion disposed generally over and insulated from a surface of said floating gate.

17. The device of claim 1, wherein a portion of said control gate has a thickness permitting ballistic charges transport therethrough.

18. The device of claim 16, wherein said second portion of said control gate is generally thinner than said first portion

19. The device of claim 16, wherein said second portion of said control gate has generally a concave shaped structure.

20. The device of claim 16, wherein said second portion of said control gate has generally a convex shaped structure.

21. The device of claim 16, wherein said second portion of said control gate has generally a semi-recessed trench shaped structure.

22. The device of claim 1, further comprising an insulating layer between said tunneling gate and said control gate, said insulating layer having a thickness permitting quantum mechanical tunneling of charges therethrough.

23. The device of claim 22, wherein said insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

24. The device of claim 22, wherein said insulating layer includes:

a first portion generally disposed over said first portion of said control gate region; and

a second portion generally disposed over the entire second portion of said control gate region.

25. The device of claim 22, wherein the quantum mechanical tunneling is the Fowler-Nordheim tunneling

26. The device of claim 22, wherein the quantum mechanical tunneling is the direct-tunneling mechanism

27. The device of claim 24, wherein said second portion of insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

28. The device of claim 1, wherein said control gate is a heavily doped p-type semiconductor material.

29. The device of claim 1, wherein said tunneling gate is a heavily doped p-type semiconductor material

30. The device of claim 22, wherein said control gate is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

31. The device of claim 22, wherein the tunneling gate is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of the insulating layer

32. An array of electrically programmable and erasable memory devices comprising:

a bulk material;

a first layer of semiconductor material over said bulk material and having a first conductivity type;

spaced apart isolation regions formed in said first layer which are generally parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;

spaced apart drain-lines extend in said first direction with each of said drain-line formed in at least a portion of said active region and next to the surface of said first layer;

each of said active regions including a plurality of memory cells, each of the memory cells comprising;

a first region formed in between said bulk material and said first layer, and having a second conductivity type;

a trench formed into a surface of said first layer and having a sidewall and a bottom;

a second region formed in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type;

a channel region in said first layer between said first region and said second region, and extending generally along said sidewall of said trench;

an electrically conductive floating gate disposed adjacent to and insulated from said channel region;

an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate; and

an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.

33. The array of device of claim 32, wherein said bulk material is a semiconductor material having the first conductivity type.

34. The array of devices of claim 32, further comprising:

a plurality of said trenches arranged in an array of columns extending in the first direction and rows in a second direction generally perpendicular to the first direction.

35. The array of devices of claim 34, wherein each column of said trenches is generally centered to one of said drain-lines.

36. The array of devices of claim 32, further comprising:

a plurality of parallel spaced apart control gate lines of conductive material each extending across said active regions and isolation regions in a second direction generally perpendicular to the first direction;

wherein each of the control gate lines is electrically connected to some of said control gates of said memory devices.

37. The array of devices of claim 32, further comprising:

a plurality of parallel spaced apart tunneling line blocks of conductive material each extending in the first direction and electrically connected to some of said tunneling gates of said memory devices.

38. The array of devices of claim 32, wherein for each of the memory cells:

said control gate and said tunneling gate overlap with each other at an overlapping region; and

at least a portion of said floating gate is disposed under the overlapping region.

39. The array of devices of claim 32, wherein for each of the memory cells, said second region is electrically connected to at least a portion of one of said drain-lines.

40. The array of devices of claim 32, further comprising:

a plurality of parallel spaced apart source lines of conductive material each electrically connected to some of said first regions of said memory devices.

41. The array of devices of claim 32, wherein for each of the memory cells, said trench extends through said second region and said first layer with said bottom formed within said first region.

42. The array of devices of claim 32, wherein for each of the memory cells, said trench extends through said second region, said first layer, and said first region, with said bottom formed within said bulk material.

43. The array of devices of claim 32, wherein each of said floating gate includes:

a first portion disposed laterally adjacent to and insulated from said sidewall of one of said trenches; and

a second portion disposed over and insulated from said bottom of said one trench.

44. The array of devices of claim 32, wherein each of said floating gates includes:

a first portion disposed over and insulated from at least a portion of one of said second regions;

a second portion disposed laterally adjacent to and insulated from said sidewall of one of said trenches; and

a third portion disposed over and insulated from said bottom of said one trench.

45. The array of devices of claim 43, wherein each of the floating gate regions has a generally rectangular shaped structure.

46. The array of devices of claim 43, wherein each of said floating gates has a generally truncated “

V”

shaped structure.

47. The array of devices of claim 44, wherein each of said floating gate regions has a generally “

T”

shaped structure.

48. The array of devices of claim 32, wherein for each of said memory cells, a portion of said control gate has a thickness permitting ballistic charges transport therethrough.

49. The array of devices of claim 32, wherein for each of said memory cells, said control gate includes:

a first portion disposed generally over and insulated from at least a portion of said second region and a surface of said first layer; and

a second portion disposed generally over and insulated from a surface of said floating gate, and having a thickness permitting ballistic charges transport therethrough.

50. The array of devices of claim 49, wherein for each of said control gates, said second portion is generally thinner than said first portion.

51. The array of devices of claim 49, wherein each of said second portions of said control gates has generally a concave shaped structure.

52. The array of devices of claim 49, wherein each of said second portions of said control gates has generally a convex shaped structure.

53. The array of devices of claim 49, wherein each of said second portions of said control gates has generally a semi-recessed trench shaped structure.

54. The array of devices of claim 32, wherein each of said memory cells further comprising an insulating layer between said tunneling gate and said control gate, said insulating layer having a thickness permitting quantum mechanical tunneling of charges therethrough.

55. The array of devices of claim 54, wherein said insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

56. The array of devices of claim 54, wherein for each of the memory cells, said insulating layer includes:

a first portion disposed generally over said first portion of said control gate; and

a second portion disposed generally over said second portion of said control gate.

57. The array of devices of claim 54, wherein the quantum mechanical tunneling is the Fowler-Nordheim tunneling.

58. The array of devices of claim 54, wherein the quantum mechanical tunneling is the direct-tunneling mechanism.

59. The array of devices of claim 56, wherein for each of said memory cells, said second portion of said insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

60. The array of devices of claim 32, wherein each of said control gates is a heavily doped p-type semiconductor material.

61. The array of devices of claim 32, wherein each of said tunneling gates is a heavily doped p-type semiconductor material.

62. The array of devices of claim 54, wherein each of said control gates is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

63. The array of devices of claim 54, wherein each of said tunneling gates is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

64. The array of devices of claim 32;

wherein each of said isolation regions has a block of insulator.

65. A method of forming an electrically erasable and programmable read only memory cell comprising the steps of:

forming a first layer of semiconductor material over a bulk material and having a first conductivity type;

forming a first region in between said bulk material and said first layer, and having a second conductivity type;

forming a trench into a surface of said first layer and having a sidewall and a bottom;

forming a second region in said first layer, laterally adjacent to an upper portion of said trench, and having the second conductivity type;

forming a channel region in said first layer between said first region and said second region, and extending generally along said sidewall of said trench;

forming an electrically conductive floating gate disposed adjacent to and insulated from said channel region;

forming an electrically conductive control gate having at least a portion thereof disposed over and insulated from said floating gate; and

forming an electrically conductive tunneling gate disposed over and insulated from at least a portion of said control gate.

66. The method of claim 65, wherein at least a portion of said floating gate is disposed laterally adjacent to said channel region.

67. The method of claim 65, wherein:

said sidewall of said trench is generally perpendicular to the surface of said first layer; and

said bottom of said trench is generally parallel to the surface of said first layer

68. The method of claim 65, wherein said trench extends through said first layer with said bottom formed within said first region.

69. The method of claim 65, wherein said trench extends through said first layer and said first region with said bottom formed within said bulk material.

70. The method of claim 65, wherein said floating gate includes:

a first portion disposed laterally adjacent to and insulated from said sidewall of said trench; and

a second portion disposed over and insulated from said bottom of said trench.

71. The method of claim 65, wherein said floating gate includes:

a first portion disposed over and insulated from at least a portion of said second region;

a second portion disposed laterally adjacent to and insulated from said sidewall of said trench; and

a third portion disposed over and insulated from said bottom of said trench.

72. The method of claim 65, further comprising the steps of forming a first insulating layer having a first portion disposed over said second region and a surface of said first layer, and a second portion disposed over said bottom and laterally adjacent to said sidewall of said trench.

73. The method of claim 65, wherein:

said control gate and said tunneling gate overlap with each other at an overlapping region; and

at least a portion of said floating gate is disposed under the overlapping region.

74. The method of claim 70, wherein said floating gate has a generally rectangular shaped structure.

75. The method of claim 70, wherein said floating gate has a generally “

V”

shaped structure.

76. The method of claim 71, wherein said floating gate has a generally “

T”

shaped structure.

77. The method of claim 65, wherein said control gate includes:

a first portion disposed generally over and insulated from at least a portion of said second region and a surface of said first layer; and

a second portion disposed generally over and insulated from a surface of said floating gate.

78. The method of claim 65, wherein a portion of said control gate has a thickness permitting ballistic charges transport therethrough.

79. The method of claim 77, wherein said second portion of said control gate is generally thinner than said first portion

80. The method of claim 77, wherein said second portion of said control gate has generally a concave shaped structure.

81. The method of claim 77, wherein said second portion of said control gate has generally a convex shaped structure.

82. The method of claim 77, wherein said second portion of said control gate has generally a semi-recessed trench shaped structure.

83. The method of claim 65, further comprising the steps of forming an insulating layer between said tunneling gate and said control gate, said insulating layer having a thickness permitting quantum mechanical tunneling of charges therethrough.

84. The method of claim 83, wherein said insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

85. The method of claim 83, wherein said insulating layer includes:

a first portion generally disposed over said first portion of said control gate region; and

a second portion generally disposed over the entire second portion of said control gate region.

86. The method of claim 83, wherein the quantum mechanical tunneling is the Fowler-Nordheim tunneling

87. The method of claim 83, wherein the quantum mechanical tunneling is the direct-tunneling mechanism

88. The method of claim 85, wherein said second portion of insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

89. The method of claim 65, wherein said control gate is a heavily doped p-type semiconductor material.

90. The method of claim 65, wherein said tunneling gate is a heavily doped p-type semiconductor material

91. The method of claim 83, wherein said control gate is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

92. The method of claim 83, wherein the tunneling gate is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of the insulating layer

93. A method of forming an array of electrically programmable and erasable memory devices comprising the steps of:

forming spaced apart isolation regions in a first layer of semiconductor material, which is over a bulk material and having a first conductivity type, wherein said isolation regions are generally parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions;

forming spaced apart drain-lines extending in the first direction with each of said drain-lines formed in at least a portion of one of said active regions and next to a surface of said first layer;

forming a plurality of trenches into the surface of said first layer and arranged in an array of columns extending in the first direction and rows in a second direction generally perpendicular to the first direction;

wherein each of said trenches has a sidewall and a bottom;

forming a plurality of first regions each in between said bulk material and said first layer, and having a second conductivity type;

forming a plurality of second regions each laterally adjacent to an upper portion of one of said trenches, and having the second conductivity type;

forming a plurality of channel regions in said first layer each extending between one of said first regions and one of said second regions, and extending generally along said sidewall of one of said trenches;

forming a plurality of electrically conductive floating gates each disposed adjacent to and insulated from one of said channel regions;

forming a plurality of electrically conductive control gates each having at least a portion thereof disposed over and insulated from one of said floating gates; and

forming a plurality of electrically conductive tunneling gates each disposed over and insulated from at least a portion of one of said control gates.

94. The method of claim 93, wherein each column of said trenches is generally centered to one of said drain-lines.

95. The method of claim 93, further comprising the steps of forming:

a plurality of parallel spaced apart control gate lines of conductive material each extending across said active regions and said isolation regions in a second direction generally perpendicular to the first direction;

wherein each of said control gate lines is electrically connected to some of said control gates of said memory devices.

96. The method of claim 93, further comprising the steps of forming:

a plurality of parallel spaced apart tunneling line blocks of conductive material each extending in the first direction and electrically connected to some of said tunneling gates of said memory devices.

97. The method of claim 93, wherein each of said control gates and said tunneling gates overlap with each other at an overlapping region, wherein each of said floating gates is disposed under one of said overlapping regions.

98. The method of claim 93, wherein each of said second regions is formed to electrically connect to at least a portion of one of said drain-lines.

99. The method of claim 93, further comprising the steps of forming:

a plurality of parallel spaced apart source lines of conductive material each electrically connected to some of said first regions of said memory devices.

100. The method of claim 93, wherein each of said trenches extends through one of said second regions and said first layer with said bottom formed within one of said first regions.

101. The method of claim 93, wherein each of said trenches extends through one of said second regions, said first layer, and one of said first regions, with said bottom formed within said bulk material.

102. The method of claim 93, wherein each of said floating gate includes:

a first portion disposed laterally adjacent to and insulated from said sidewall of one of said trenches; and

a second portion disposed over and insulated from said bottom of said one trench.

103. The method of claim 93, wherein each of said floating gate includes:

a first portion disposed over and insulated from at least a portion of one of said second regions;

a second portion disposed laterally adjacent to and insulated from said sidewall of one of said trenches; and

a third portion disposed over and insulated from said bottom of said one trench.

104. The method of claim 102, wherein each of the floating gate regions has a generally rectangular shaped structure.

105. The method of claim 102, wherein each of said floating gates has a generally truncated “

V”

shaped structure.

106. The method of claim 103, wherein each of said floating gate regions has a generally “

T”

shaped structure.

107. The method of claim 93, wherein a portion of each of said control gates has a thickness permitting ballistic charges transport therethrough.

108. The method of claim 93, wherein each of said control gates includes:

a first portion disposed generally over and insulated from at least a portion of one of said second regions and a surface of said first layer; and

a second portion disposed generally over and insulated from a surface of one of said floating gates, and having a thickness permitting ballistic charges transport therethrough.

109. The method of claim 108, wherein for each of said control gates, said second portion is generally thinner than said first portion.

110. The method of claim 108, wherein said second portion of each of said control gates has generally a concave shaped structure.

111. The method of claim 108, wherein said second portion of each of said control gates has generally a convex shaped structure.

112. The method of claim 108, wherein said second portion of each of said control gates has generally a semi-recessed trench shaped structure.

113. The method of claim 93, further comprising the steps of forming an insulating layer between each of said tunneling gates and each of said control gates, said insulating layer having a thickness permitting quantum mechanical tunneling of charges therethrough.

114. The method of claim 113, wherein said insulating layer is a silicon oxynitride layer having a fractional oxide in the range between about 70% and about 90%.

115. The method of claim 113, wherein the quantum mechanical tunneling is the Fowler-Nordheim tunneling.

116. The method of claim 113, wherein the quantum mechanical tunneling is the direct-tunneling mechanism.

117. The method of claim 93, wherein each of said control gates is a heavily doped p-type semiconductor material.

118. The method of claim 93, wherein each of said tunneling gates is a heavily doped p-type semiconductor material.

119. The method of claim 113, wherein each of said control gates is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

120. The method of claim 113, wherein each of said tunneling gates is a metal having a work function with the Fermi-level lies generally in the middle of the energy band gap of said insulating layer.

121. The method of claim 93, wherein each of said isolation regions is formed to include a block of insulator.

122. A method of operating an electrically programmable and erasable memory device having an electrical conductive floating gate formed in a trench in a semiconductor substrate, an electrical conductive control gate having a portion disposed over and insulated from said floating gate, and an electrical conductive tunneling gate disposed over and insulated from said control gate by an insulating layer to form a multi-layers structure permitting both electron and hole charges tunneling through said insulating layer at a generally similar rate. Spaced apart source and drain regions are formed with said source region disposed adjacent to and insulated from a lower portion of said floating gate, and with said drain region disposed adjacent to and insulated from an upper portion of said floating gate with a channel region formed therebetween and along a sidewall of said trench, the method comprising the steps of:

placing a positive voltage on said drain region to capacitively couple a positive voltage onto said floating gate; and

placing a voltage on said tunneling gate that is sufficiently negative relative to a voltage of said control gate to emanate electrons from said tunneling gate and to emanate holes from said control gate to permit electrons and holes tunneling through said insulating layer at a generally similar rate and in opposite directions with electrons having sufficient energy to transport through said control gate, and onto said floating gate via ballistic carrier transport mechanism.

123. The method of claim 122, further comprising the steps of:

placing a negative voltage on said drain region to capacitively couple a negative voltage onto the floating gate;

placing a voltage on said tunneling gate that is sufficiently positive relative to a voltage of said control gate to emanate holes from said tunneling gate and to emanate electrons from said control gate to permit electrons and holes tunneling through said insulating layer at a generally similar rate and in opposite directions with holes having sufficient energy to transport through said control gate, and onto said floating gate via ballistic carrier transport mechanism.

124. A method of operating an electrically programmable and erasable non-volatile memory cell having at least two states, and including an electrical conductive floating gate formed in a semiconductor substrate, an electrical conductive control gate having a portion disposed over and insulated from said floating gate, and an electrical conductive tunneling gate disposed over and insulated from said control gate by an insulating layer to form a multi-layers structure permitting both electron and hole charges tunneling through said insulating layer at a similar rate. Spaced apart source and drain regions are formed adjacent to and insulated from said floating gate with a channel region defined therebetween and insulated from said floating gate, the method comprising the step of:

establishing each of said states of the memory cell by emanating electrons from said tunneling gate and emanating holes from said control gate to permit electrons and holes transporting through said insulating layer at a generally similar rate and in opposite directions with electrons having sufficient energy to transport through said control gate and onto said floating gate via ballistic carrier transport mechanism; and

establishing each of said states of the memory cell by emanating holes from said tunneling gate and emanating electrons from said control gate to permit electrons and holes transporting through said insulating layer at a generally similar rate and in opposite directions with holes having sufficient energy to transport through said control gate and onto said floating gate via ballistic carrier transport mechanism.