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Nanoelectronic interconnection and addressing

  • US 20040248381A1
  • Filed: 11/25/2003
  • Published: 12/09/2004
  • Est. Priority Date: 11/01/2000
  • Status: Abandoned Application
First Claim
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1. A method for manufacturing a wafer having conductors separated by distances in the range of from about 1 to about 100 nm for nanoscale electronics, comprising the steps of depositing sequential layers of conductors, semiconductors and/or dielectrics on a sheath substrate at thicknesses in the range of from about 1 to about 100 nm to form a layered wafer boule patterning at least some of the conductor or semiconductor layers for backside addressing;

  • cross cutting the wafer boule, and polishing the front and back surfaces to provide a nanoscale wafer.

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