Nanoelectronic interconnection and addressing

• US 20040248381A1
• Filed: 11/25/2003
• Published: 12/09/2004
• Est. Priority Date: 11/01/2000
• Status: Abandoned Application

• Current Assignee: James J. Myrick
• Original Assignee: James J. Myrick
• Inventors: Myrick, James J.
• Application Number:
  US10/479,032
• Publication Number:
  US 20040248381A1
• Time in Patent Office: Days
• US Class Current: 438/460
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H10K 10/00 Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers integrated devices or assemblies of multiple devices H10K19/00
• CPC Class Codes: H10K 10/20 Organic diodes
• CPC Class Codes: H10K 10/701 Organic molecular electronic devices
• CPC Class Codes: H10K 10/82 Electrodes
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10K 85/40 Organosilicon compounds, e.g. TIPS pentacene
• CPC Class Codes: H10K 85/60 Organic compounds having low molecular weight H10K85/10 - H10K85/50 take precedence
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
• CPC Class Codes: H10K 85/626 containing more than one polycyclic condensed aromatic rings, e.g. bis-anthracene
• CPC Class Codes: H10K 85/655 comprising only sulfur as heteroatom

Abstract

Methods and devices relating to nanoscale electronics, including fabrication and addressing of molecular electronics.

Claims

1. A method for manufacturing a wafer having conductors separated by distances in the range of from about 1 to about 100 nm for nanoscale electronics, comprising the steps of

depositing sequential layers of conductors, semiconductors and/or dielectrics on a sheath substrate at thicknesses in the range of from about 1 to about 100 nm to form a layered wafer boule patterning at least some of the conductor or semiconductor layers for backside addressing;

cross cutting the wafer boule, and polishing the front and back surfaces to provide a nanoscale wafer.

2. A method in accordance with claim 1 wherein one or more molecular electronic components is self-assembled on the front surface of the nanoscale wafer.

3. A method in accordance with claim 2 wherein two nanoscale wafers are assembled adjacent each other to define molecular electronic zones such as addressable memory or logic gates.

4. A method in accordance with claim 2 wherein at least one of the molecular electronic compounds is a multi-dentate, multi-terminal electronic compound with multiple terminals each with a functional attachment group having a spacing and position corresponding to the spacing and position of a corresponding reactive self-assembly surface on a wafer face or adjacent wafer face, for the respective functional group.