Apparatus and method for monitoring high impedance failures in chip interconnects

• US 20040249612A1
• Filed: 06/04/2003
• Published: 12/09/2004
• Est. Priority Date: 06/04/2003
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Co. (HP Inc.)
• Inventors: Pomaranski, Ken G., Shidla, Dale J., Barr, Andrew H.
• Granted Patent: US 6,895,353 B2
• Time in Patent Office: Days
• US Class Current: 702/188
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66

Abstract

A method and corresponding apparatus for monitoring high impedance failures in chip interconnects use monitoring circuitry on a chip to provide accurate and pro-active prediction of interconnect failures. The apparatus may include a resistance continuity monitoring circuit (RCMC), and a signal path connecting a representative set of pins to the RCMC. The RCMC measures the resistance of a connection of the representative set of pins with a circuit board during system operation and outputs a measured resistance data. The apparatus further includes additional analog-to-digital (A/D) hardware to perform an analog to digital conversion of the measured resistance data. The apparatus further includes a system interface for connecting the monitoring circuitry with other system management devices. The method then performs an algorithm on the measured resistance data, potentially warning of likely interconnect failures. The algorithm may include comparing the measured resistance data with a known threshold resistance value. Alternatively, the method displays and logs the measured resistance data for further study and analysis.

Claims

1. An apparatus for monitoring high impedance failures in system interconnects, comprising:

monitoring circuitry located on a chip, comprising;

a resistance continuity monitoring circuit (RCMC), wherein the RCMC measures the resistance of a connection of a representative set of pins on the chip with a circuit board, outputting an analog measured resistance data;

a signal path connecting the representative set of pins to the RCMC; and

a system interface for connecting the RCMC with other system components;

wherein the monitoring circuitry converts the analog measured resistance data to digital resistance data and displays the digital resistance data on an output device.

2. The apparatus of claim 1, wherein the chip is an application specific integrated circuit.

3. The apparatus of claim 1, further comprising:

an analog-to-digital (A/D) converter, wherein the A/D converter converts the analog measured resistance data to the digital resistance data.

4. The apparatus of claim 3, wherein the A/D converter and the RCMC are integrated as a combined circuit.

5. The apparatus of claim 1, wherein the monitoring circuitry logs the digital resistance data.

6. The apparatus of claim 1, wherein the chip is partitioned into a plurality of pin areas and each pin area includes a representative set of pins, the apparatus further comprising a plurality of signal paths, wherein each signal path connects a representative set of pins to the RCMC and the RCMC measures the resistance of a connection of each representative set of pins with the circuit board.

7. The apparatus of claim 6, wherein the chip includes four corners and a center and partitioned into five areas, with one pin area in each of the four corners and the center.

8. The apparatus of claim 1, wherein the chip is partitioned into a plurality of pin areas and each pin area includes a representative set of pins, wherein the signal path connects a plurality of representative set of pins in one or more pin areas to the RCMC and the RCMC measures the resistance of a connection of the plurality representative set of pins with the circuit board.

9. The apparatus of claim 1, wherein the other system components include a processor that runs instructions controlling the operation of the RCMC.

10. The apparatus of claim 9, wherein the processor processes the digital resistance data.

13. The method of claim 10, wherein the chip is partitioned into a plurality of pin areas and each pin area includes a representative set of pins, and the method further comprising a step of:

routing a signal path from a representative set of pins in each pin area to a RCMC, wherein the RCMC measures the resistance of a connection of each representative set of pins with the circuit board.

14. The method of claim 10, wherein the chip is partitioned into a plurality of pin areas and each pin area includes a representative set of pins, and the method further comprising a step of:

routing a signal path from a plurality representative set of pins in one or more pin areas to a RCMC, wherein the RCMC measures the resistance of a connection of the plurality representative set of pins with the circuit board.

15. The method of claim 10, further comprising the steps of:

partitioning the chip into pin areas, wherein each pin area includes pins connecting the chip to a circuit board; and

selecting the representative set of pins in a pin area.

16. The method of claim 10, wherein chip includes four corners and a center and wherein the partitioning step partitions the chip into five pin areas, one pin area for each of the four corners and the center.

17. The method of claim 10, further comprising a step of:

communicating the measured resistance data to system management devices, wherein the system management devices execute the algorithm performing step.

18. The method of claim 10, further comprising a step of:

logging the digital resistance data.

11. A method for detecting high impedance failures in system interconnects, comprising steps of:

measuring the resistance of a connection of a representative set of pins on a chip to a circuit board using monitoring circuitry located on the chip, wherein the measuring step produces an analog measured resistance data;

converting the analog measured resistance data to digital resistance data;

displaying the digital resistance data on an output device; and

performing an algorithm on the digital resistance data.

12. The method of claim 11, further comprising a step of:

taking appropriate action based on results of the algorithm performed on the digital resistance data.

19. A computer-readable medium comprising instructions for monitoring high impedance failures in system interconnects, the instructions comprising:

measuring the resistance of a connection of a representative set of pins on a chip to a circuit board using monitoring circuitry located on the chip, wherein the measuring step produces an analog measured resistance data;

converting the analog measured resistance data to digital resistance data;

displaying the digital resistance data on an output device; and

performing an algorithm on the digital resistance data.

20. The computer-readable medium of claim 19, further comprising instructions for:

communicating the measured resistance data to a system management devices, wherein the system management devices execute the algorithm performing step.